Re: [perfmon2] installing on Mac OS X

[Giovanni A. <bra...@gm...>]

Hi Eranian,

Thank you, now is clear. Then I have no choice but to get a Linux box going.

Best regards,
Giovanni

On Apr 26, 2012, at 2:06 PM, stephane eranian wrote:

> Hi,
> 
> The fact that you can compile and execute certain test programs does not mean you're actually measuring stuff.
> The validation tests and check_events are just testing the encoding of events.
> They are measuring. The fact that it detects your CPU type means it recognized your CPU model. To measure something you need to pass the event encoding to the Mac is kernel. However the Mac kernel interface to the hardware counters is not public AFAIK. 
> The encoding shown by the test program is solely based on HW specs not OS API.
> In summary, you cannot use liblfm4 as it is today to measure events on Mac os x. I same sure the core (generic code ) compiles but that's all I can do at this point.
> On Apr 26, 2012 4:22 AM, "Giovanni Azua" <bra...@gm...> wrote:
> 
> On Apr 25, 2012, at 7:14 PM, stephane eranian wrote:
>>> 
>>> Do you confirm that perfmon2 then works for Mac OS X? and that the tests passing is not mere coincidence?
>>> 
>> No it does not.
>> perfmon2 or perf_event do not work on Mac OS X.
>> 
>> The tests are just validating the event tables, they are not measuring anything.
> 
> OK interesting. 
> 
> Now if I run your check_events example (I have Intel Core Duo) I get the first output below. I'm mostly interested in FLOPS and seems not to be supported while it is an Intel Core Duo event ... can you please clarify? I checked the following two are supported and output a valid result using check_events CPU_CLK_UNHALTED and DTLB_MISSES.
> 
> Running showevtinfo produces the second output below which means those counters are available for measuring right? 
> 
> Are these also a "fake" test?
> 
> Thanks in advance,
> Best regards,
> Giovanni
> 
> /Users/bravegag/code/libpfm-4.2.0/examples$ ./check_events MUL
> Supported PMU models:
> 	[7, netburst, "Pentium4"]
> 	[8, netburst_p, "Pentium4 (Prescott)"]
> 	[11, core, "Intel Core"]
> 	[14, atom, "Intel Atom"]
> 	[15, nhm, "Intel Nehalem"]
> 	[16, nhm_ex, "Intel Nehalem EX"]
> 	[17, nhm_unc, "Intel Nehalem uncore"]
> 	[18, ix86arch, "Intel X86 architectural PMU"]
> 	[52, wsm, "Intel Westmere (single-socket)"]
> 	[53, wsm_dp, "Intel Westmere DP"]
> 	[54, wsm_unc, "Intel Westmere uncore"]
> 	[55, amd64_k7, "AMD64 K7"]
> 	[56, amd64_k8_revb, "AMD64 K8 RevB"]
> 	[57, amd64_k8_revc, "AMD64 K8 RevC"]
> 	[58, amd64_k8_revd, "AMD64 K8 RevD"]
> 	[59, amd64_k8_reve, "AMD64 K8 RevE"]
> 	[60, amd64_k8_revf, "AMD64 K8 RevF"]
> 	[61, amd64_k8_revg, "AMD64 K8 RevG"]
> 	[62, amd64_fam10h_barcelona, "AMD64 Fam10h Barcelona"]
> 	[63, amd64_fam10h_shanghai, "AMD64 Fam10h Shanghai"]
> 	[64, amd64_fam10h_istanbul, "AMD64 Fam10h Istanbul"]
> 	[68, snb, "Intel Sandy Bridge"]
> 	[69, amd64_fam14h_bobcat, "AMD64 Fam14h Bobcat"]
> 	[70, amd64_fam15h_interlagos, "AMD64 Fam15h Interlagos"]
> 	[71, snb_ep, "Intel Sandy Bridge EP"]
> Detected PMU models:
> 	[11, core, "Intel Core"]
> 	[18, ix86arch, "Intel X86 architectural PMU"]
> Total events: 2010 available, 140 supported
> Requested Event: MUL
> Actual    Event: core::MUL:k=1:u=1:e=0:i=0:c=0
> PMU            : Intel Core
> IDX            : 23068695
> Codes          : 0x530012
> /Users/bravegag/code/libpfm-4.2.0/examples$ ./check_events FLOPS
> Supported PMU models:
> 	[7, netburst, "Pentium4"]
> 	[8, netburst_p, "Pentium4 (Prescott)"]
> 	[11, core, "Intel Core"]
> 	[14, atom, "Intel Atom"]
> 	[15, nhm, "Intel Nehalem"]
> 	[16, nhm_ex, "Intel Nehalem EX"]
> 	[17, nhm_unc, "Intel Nehalem uncore"]
> 	[18, ix86arch, "Intel X86 architectural PMU"]
> 	[52, wsm, "Intel Westmere (single-socket)"]
> 	[53, wsm_dp, "Intel Westmere DP"]
> 	[54, wsm_unc, "Intel Westmere uncore"]
> 	[55, amd64_k7, "AMD64 K7"]
> 	[56, amd64_k8_revb, "AMD64 K8 RevB"]
> 	[57, amd64_k8_revc, "AMD64 K8 RevC"]
> 	[58, amd64_k8_revd, "AMD64 K8 RevD"]
> 	[59, amd64_k8_reve, "AMD64 K8 RevE"]
> 	[60, amd64_k8_revf, "AMD64 K8 RevF"]
> 	[61, amd64_k8_revg, "AMD64 K8 RevG"]
> 	[62, amd64_fam10h_barcelona, "AMD64 Fam10h Barcelona"]
> 	[63, amd64_fam10h_shanghai, "AMD64 Fam10h Shanghai"]
> 	[64, amd64_fam10h_istanbul, "AMD64 Fam10h Istanbul"]
> 	[68, snb, "Intel Sandy Bridge"]
> 	[69, amd64_fam14h_bobcat, "AMD64 Fam14h Bobcat"]
> 	[70, amd64_fam15h_interlagos, "AMD64 Fam15h Interlagos"]
> 	[71, snb_ep, "Intel Sandy Bridge EP"]
> Detected PMU models:
> 	[11, core, "Intel Core"]
> 	[18, ix86arch, "Intel X86 architectural PMU"]
> Total events: 2010 available, 140 supported
> check_events: cannot encode event FLOPS: event not found
> 
> 
> Supported PMU models:
> 	[7, netburst, "Pentium4"]
> 	[8, netburst_p, "Pentium4 (Prescott)"]
> 	[11, core, "Intel Core"]
> 	[14, atom, "Intel Atom"]
> 	[15, nhm, "Intel Nehalem"]
> 	[16, nhm_ex, "Intel Nehalem EX"]
> 	[17, nhm_unc, "Intel Nehalem uncore"]
> 	[18, ix86arch, "Intel X86 architectural PMU"]
> 	[52, wsm, "Intel Westmere (single-socket)"]
> 	[53, wsm_dp, "Intel Westmere DP"]
> 	[54, wsm_unc, "Intel Westmere uncore"]
> 	[55, amd64_k7, "AMD64 K7"]
> 	[56, amd64_k8_revb, "AMD64 K8 RevB"]
> 	[57, amd64_k8_revc, "AMD64 K8 RevC"]
> 	[58, amd64_k8_revd, "AMD64 K8 RevD"]
> 	[59, amd64_k8_reve, "AMD64 K8 RevE"]
> 	[60, amd64_k8_revf, "AMD64 K8 RevF"]
> 	[61, amd64_k8_revg, "AMD64 K8 RevG"]
> 	[62, amd64_fam10h_barcelona, "AMD64 Fam10h Barcelona"]
> 	[63, amd64_fam10h_shanghai, "AMD64 Fam10h Shanghai"]
> 	[64, amd64_fam10h_istanbul, "AMD64 Fam10h Istanbul"]
> 	[68, snb, "Intel Sandy Bridge"]
> 	[69, amd64_fam14h_bobcat, "AMD64 Fam14h Bobcat"]
> 	[70, amd64_fam15h_interlagos, "AMD64 Fam15h Interlagos"]
> 	[71, snb_ep, "Intel Sandy Bridge EP"]
> Detected PMU models:
> 	[11, core, "Intel Core", 133 events, 1 max encoding, 5 counters, core PMU]
> 	[18, ix86arch, "Intel X86 architectural PMU", 7 events, 1 max encoding, 5 counters, core PMU]
> Total events: 2010 available, 140 supported
> #-----------------------------
> IDX	 : 23068672
> PMU name : core (Intel Core)
> Name     : UNHALTED_CORE_CYCLES
> Equiv	 : None
> Flags    : None
> Desc     : Count core clock cycles whenever the clock signal on the specific core is running (not halted)
> Code     : 0x3c
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068673
> PMU name : core (Intel Core)
> Name     : INSTRUCTION_RETIRED
> Equiv	 : None
> Flags    : None
> Desc     : Count the number of instructions at retirement
> Code     : 0xc0
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068674
> PMU name : core (Intel Core)
> Name     : INSTRUCTIONS_RETIRED
> Equiv	 : INSTRUCTION_RETIRED
> Flags    : None
> Desc     : This is an alias from INSTRUCTION_RETIRED
> Code     : 0xc0
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068675
> PMU name : core (Intel Core)
> Name     : UNHALTED_REFERENCE_CYCLES
> Equiv	 : None
> Flags    : None
> Desc     : Unhalted reference cycles
> Code     : 0x300
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> #-----------------------------
> IDX	 : 23068676
> PMU name : core (Intel Core)
> Name     : LLC_REFERENCES
> Equiv	 : None
> Flags    : None
> Desc     : Count each request originating equiv the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESI
> Code     : 0x4f2e
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068677
> PMU name : core (Intel Core)
> Name     : LAST_LEVEL_CACHE_REFERENCES
> Equiv	 : LLC_REFERENCES
> Flags    : None
> Desc     : This is an alias for LLC_REFERENCES
> Code     : 0x4f2e
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068678
> PMU name : core (Intel Core)
> Name     : LLC_MISSES
> Equiv	 : None
> Flags    : None
> Desc     : Count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATE
> Code     : 0x412e
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068679
> PMU name : core (Intel Core)
> Name     : LAST_LEVEL_CACHE_MISSES
> Equiv	 : LLC_MISSES
> Flags    : None
> Desc     : This is an alias for LLC_MISSES
> Code     : 0x412e
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068680
> PMU name : core (Intel Core)
> Name     : BRANCH_INSTRUCTIONS_RETIRED
> Equiv	 : BR_INST_RETIRED:ANY
> Flags    : None
> Desc     : Count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.
> Code     : 0xc4
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068681
> PMU name : core (Intel Core)
> Name     : MISPREDICTED_BRANCH_RETIRED
> Equiv	 : BR_INST_RETIRED_MISPRED
> Flags    : [precise] 
> Desc     : Count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware.
> Code     : 0xc5
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068682
> PMU name : core (Intel Core)
> Name     : RS_UOPS_DISPATCHED_CYCLES
> Equiv	 : None
> Flags    : None
> Desc     : Cycles micro-ops dispatched for execution
> Code     : 0xa1
> Umask-00 : 0x01 : PMU : [PORT_0] : None : On port 0
> Umask-01 : 0x02 : PMU : [PORT_1] : None : On port 1
> Umask-02 : 0x04 : PMU : [PORT_2] : None : On port 2
> Umask-03 : 0x08 : PMU : [PORT_3] : None : On port 3
> Umask-04 : 0x10 : PMU : [PORT_4] : None : On port 4
> Umask-05 : 0x20 : PMU : [PORT_5] : None : On port 5
> Umask-06 : 0x3f : PMU : [ANY] : [default] : Alias to PORT_0:PORT_1:PORT_2:PORT_3:PORT_4:PORT_5
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068683
> PMU name : core (Intel Core)
> Name     : RS_UOPS_DISPATCHED
> Equiv	 : None
> Flags    : None
> Desc     : Number of micro-ops dispatched for execution
> Code     : 0xa0
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068684
> PMU name : core (Intel Core)
> Name     : RS_UOPS_DISPATCHED_NONE
> Equiv	 : RS_UOPS_DISPATCHED:i=1:c=1
> Flags    : None
> Desc     : Number of of cycles in which no micro-ops is dispatched for execution
> Code     : 0x18000a0
> #-----------------------------
> IDX	 : 23068685
> PMU name : core (Intel Core)
> Name     : LOAD_BLOCK
> Equiv	 : None
> Flags    : None
> Desc     : Loads blocked
> Code     : 0x3
> Umask-00 : 0x02 : PMU : [STA] : None : Loads blocked by a preceding store with unknown address
> Umask-01 : 0x04 : PMU : [STD] : None : Loads blocked by a preceding store with unknown data
> Umask-02 : 0x08 : PMU : [OVERLAP_STORE] : None : Loads that partially overlap an earlier store, or 4K equived with a previous store
> Umask-03 : 0x10 : PMU : [UNTIL_RETIRE] : None : Loads blocked until retirement
> Umask-04 : 0x20 : PMU : [L1D] : None : Loads blocked by the L1 data cache
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068686
> PMU name : core (Intel Core)
> Name     : SB_DRAIN_CYCLES
> Equiv	 : None
> Flags    : None
> Desc     : Cycles while stores are blocked due to store buffer drain
> Code     : 0x104
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068687
> PMU name : core (Intel Core)
> Name     : STORE_BLOCK
> Equiv	 : None
> Flags    : None
> Desc     : Cycles while store is waiting
> Code     : 0x4
> Umask-00 : 0x02 : PMU : [ORDER] : None : Cycles while store is waiting for a preceding store to be globally observed
> Umask-01 : 0x08 : PMU : [SNOOP] : None : A store is blocked due to a conflict with an external or internal snoop
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068688
> PMU name : core (Intel Core)
> Name     : SEGMENT_REG_LOADS
> Equiv	 : None
> Flags    : None
> Desc     : Number of segment register loads
> Code     : 0x6
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068689
> PMU name : core (Intel Core)
> Name     : SSE_PRE_EXEC
> Equiv	 : None
> Flags    : None
> Desc     : Streaming SIMD Extensions (SSE) Prefetch instructions executed
> Code     : 0x7
> Umask-00 : 0x00 : PMU : [NTA] : None : Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
> Umask-01 : 0x01 : PMU : [L1] : None : Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed
> Umask-02 : 0x02 : PMU : [L2] : None : Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed
> Umask-03 : 0x03 : PMU : [STORES] : None : Streaming SIMD Extensions (SSE) Weakly-ordered store instructions executed
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068690
> PMU name : core (Intel Core)
> Name     : DTLB_MISSES
> Equiv	 : None
> Flags    : None
> Desc     : Memory accesses that missed the DTLB
> Code     : 0x8
> Umask-00 : 0x01 : PMU : [ANY] : [default] : Any memory access that missed the DTLB
> Umask-01 : 0x02 : PMU : [MISS_LD] : None : DTLB misses due to load operations
> Umask-02 : 0x04 : PMU : [L0_MISS_LD] : None : L0 DTLB misses due to load operations
> Umask-03 : 0x08 : PMU : [MISS_ST] : None : DTLB misses due to store operations
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068691
> PMU name : core (Intel Core)
> Name     : MEMORY_DISAMBIGUATION
> Equiv	 : None
> Flags    : None
> Desc     : Memory disambiguation
> Code     : 0x9
> Umask-00 : 0x01 : PMU : [RESET] : None : Memory disambiguation reset cycles
> Umask-01 : 0x02 : PMU : [SUCCESS] : None : Number of loads that were successfully disambiguated
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068692
> PMU name : core (Intel Core)
> Name     : PAGE_WALKS
> Equiv	 : None
> Flags    : None
> Desc     : Number of page-walks executed
> Code     : 0xc
> Umask-00 : 0x01 : PMU : [COUNT] : None : Number of page-walks executed
> Umask-01 : 0x02 : PMU : [CYCLES] : None : Duration of page-walks in core cycles
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068693
> PMU name : core (Intel Core)
> Name     : FP_COMP_OPS_EXE
> Equiv	 : None
> Flags    : None
> Desc     : Floating point computational micro-ops executed
> Code     : 0x10
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068694
> PMU name : core (Intel Core)
> Name     : FP_ASSIST
> Equiv	 : None
> Flags    : None
> Desc     : Floating point assists
> Code     : 0x11
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068695
> PMU name : core (Intel Core)
> Name     : MUL
> Equiv	 : None
> Flags    : None
> Desc     : Multiply operations executed
> Code     : 0x12
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068696
> PMU name : core (Intel Core)
> Name     : DIV
> Equiv	 : None
> Flags    : None
> Desc     : Divide operations executed
> Code     : 0x13
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068697
> PMU name : core (Intel Core)
> Name     : CYCLES_DIV_BUSY
> Equiv	 : None
> Flags    : None
> Desc     : Cycles the divider is busy
> Code     : 0x14
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068698
> PMU name : core (Intel Core)
> Name     : IDLE_DURING_DIV
> Equiv	 : None
> Flags    : None
> Desc     : Cycles the divider is busy and all other execution units are idle
> Code     : 0x18
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068699
> PMU name : core (Intel Core)
> Name     : DELAYED_BYPASS
> Equiv	 : None
> Flags    : None
> Desc     : Delayed bypass
> Code     : 0x19
> Umask-00 : 0x00 : PMU : [FP] : None : Delayed bypass to FP operation
> Umask-01 : 0x01 : PMU : [SIMD] : None : Delayed bypass to SIMD operation
> Umask-02 : 0x02 : PMU : [LOAD] : None : Delayed bypass to load operation
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068700
> PMU name : core (Intel Core)
> Name     : L2_ADS
> Equiv	 : None
> Flags    : None
> Desc     : Cycles L2 address bus is in use
> Code     : 0x21
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068701
> PMU name : core (Intel Core)
> Name     : L2_DBUS_BUSY_RD
> Equiv	 : None
> Flags    : None
> Desc     : Cycles the L2 transfers data to the core
> Code     : 0x23
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068702
> PMU name : core (Intel Core)
> Name     : L2_LINES_IN
> Equiv	 : None
> Flags    : None
> Desc     : L2 cache misses
> Code     : 0x24
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x30 : PMU : [ANY] : [default] : All inclusive
> Umask-03 : 0x10 : PMU : [PREFETCH] : None : Hardware prefetch only
> Umask-04 : 0x00 : PMU : [EXCL_PREFETCH] : None : Exclude hardware prefetch
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068703
> PMU name : core (Intel Core)
> Name     : L2_M_LINES_IN
> Equiv	 : None
> Flags    : None
> Desc     : L2 cache line modifications
> Code     : 0x25
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068704
> PMU name : core (Intel Core)
> Name     : L2_LINES_OUT
> Equiv	 : None
> Flags    : None
> Desc     : L2 cache lines evicted
> Code     : 0x26
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x30 : PMU : [ANY] : [default] : All inclusive
> Umask-03 : 0x10 : PMU : [PREFETCH] : None : Hardware prefetch only
> Umask-04 : 0x00 : PMU : [EXCL_PREFETCH] : None : Exclude hardware prefetch
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068705
> PMU name : core (Intel Core)
> Name     : L2_M_LINES_OUT
> Equiv	 : None
> Flags    : None
> Desc     : Modified lines evicted from the L2 cache
> Code     : 0x27
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x30 : PMU : [ANY] : [default] : All inclusive
> Umask-03 : 0x10 : PMU : [PREFETCH] : None : Hardware prefetch only
> Umask-04 : 0x00 : PMU : [EXCL_PREFETCH] : None : Exclude hardware prefetch
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068706
> PMU name : core (Intel Core)
> Name     : L2_IFETCH
> Equiv	 : None
> Flags    : None
> Desc     : L2 cacheable instruction fetch requests
> Code     : 0x28
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-03 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-04 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-05 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-06 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068707
> PMU name : core (Intel Core)
> Name     : L2_LD
> Equiv	 : None
> Flags    : None
> Desc     : L2 cache reads
> Code     : 0x29
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x30 : PMU : [ANY] : [default] : All inclusive
> Umask-03 : 0x10 : PMU : [PREFETCH] : None : Hardware prefetch only
> Umask-04 : 0x00 : PMU : [EXCL_PREFETCH] : None : Exclude hardware prefetch
> Umask-05 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-06 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-07 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-08 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-09 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068708
> PMU name : core (Intel Core)
> Name     : L2_ST
> Equiv	 : None
> Flags    : None
> Desc     : L2 store requests
> Code     : 0x2a
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-03 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-04 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-05 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-06 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068709
> PMU name : core (Intel Core)
> Name     : L2_LOCK
> Equiv	 : None
> Flags    : None
> Desc     : L2 locked accesses
> Code     : 0x2b
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-03 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-04 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-05 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-06 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068710
> PMU name : core (Intel Core)
> Name     : L2_RQSTS
> Equiv	 : None
> Flags    : None
> Desc     : L2 cache requests
> Code     : 0x2e
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x30 : PMU : [ANY] : [default] : All inclusive
> Umask-03 : 0x10 : PMU : [PREFETCH] : None : Hardware prefetch only
> Umask-04 : 0x00 : PMU : [EXCL_PREFETCH] : None : Exclude hardware prefetch
> Umask-05 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-06 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-07 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-08 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-09 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068711
> PMU name : core (Intel Core)
> Name     : L2_REJECT_BUSQ
> Equiv	 : None
> Flags    : None
> Desc     : Rejected L2 cache requests
> Code     : 0x30
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x30 : PMU : [ANY] : [default] : All inclusive
> Umask-03 : 0x10 : PMU : [PREFETCH] : None : Hardware prefetch only
> Umask-04 : 0x00 : PMU : [EXCL_PREFETCH] : None : Exclude hardware prefetch
> Umask-05 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-06 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-07 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-08 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-09 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068712
> PMU name : core (Intel Core)
> Name     : L2_NO_REQ
> Equiv	 : None
> Flags    : None
> Desc     : Cycles no L2 cache requests are pending
> Code     : 0x32
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068713
> PMU name : core (Intel Core)
> Name     : EIST_TRANS
> Equiv	 : None
> Flags    : None
> Desc     : Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions
> Code     : 0x3a
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068714
> PMU name : core (Intel Core)
> Name     : THERMAL_TRIP
> Equiv	 : None
> Flags    : None
> Desc     : Number of thermal trips
> Code     : 0xc03b
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068715
> PMU name : core (Intel Core)
> Name     : CPU_CLK_UNHALTED
> Equiv	 : None
> Flags    : None
> Desc     : Core cycles when core is not halted
> Code     : 0x3c
> Umask-00 : 0x00 : PMU : [CORE_P] : [default] : Core cycles when core is not halted
> Umask-01 : 0x01 : PMU : [BUS] : None : Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio
> Umask-02 : 0x02 : PMU : [NO_OTHER] : None : Bus cycles when core is active and the other is halted
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068716
> PMU name : core (Intel Core)
> Name     : L1D_CACHE_LD
> Equiv	 : None
> Flags    : None
> Desc     : L1 cacheable data reads
> Code     : 0x40
> Umask-00 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-01 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-02 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-03 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-04 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068717
> PMU name : core (Intel Core)
> Name     : L1D_CACHE_ST
> Equiv	 : None
> Flags    : None
> Desc     : L1 cacheable data writes
> Code     : 0x41
> Umask-00 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-01 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-02 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-03 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-04 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068718
> PMU name : core (Intel Core)
> Name     : L1D_CACHE_LOCK
> Equiv	 : None
> Flags    : None
> Desc     : L1 data cacheable locked reads
> Code     : 0x42
> Umask-00 : 0x0f : PMU : [MESI] : [default] : Alias to M_STATE:E_STATE:S_STATE:I_STATE
> Umask-01 : 0x01 : PMU : [I_STATE] : None : Invalid cacheline
> Umask-02 : 0x02 : PMU : [S_STATE] : None : Shared cacheline
> Umask-03 : 0x04 : PMU : [E_STATE] : None : Exclusive cacheline
> Umask-04 : 0x08 : PMU : [M_STATE] : None : Modified cacheline
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068719
> PMU name : core (Intel Core)
> Name     : L1D_ALL_REF
> Equiv	 : None
> Flags    : None
> Desc     : All references to the L1 data cache
> Code     : 0x143
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068720
> PMU name : core (Intel Core)
> Name     : L1D_ALL_CACHE_REF
> Equiv	 : None
> Flags    : None
> Desc     : L1 Data cacheable reads and writes
> Code     : 0x243
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068721
> PMU name : core (Intel Core)
> Name     : L1D_REPL
> Equiv	 : None
> Flags    : None
> Desc     : Cache lines allocated in the L1 data cache
> Code     : 0xf45
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068722
> PMU name : core (Intel Core)
> Name     : L1D_M_REPL
> Equiv	 : None
> Flags    : None
> Desc     : Modified cache lines allocated in the L1 data cache
> Code     : 0x46
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068723
> PMU name : core (Intel Core)
> Name     : L1D_M_EVICT
> Equiv	 : None
> Flags    : None
> Desc     : Modified cache lines evicted from the L1 data cache
> Code     : 0x47
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068724
> PMU name : core (Intel Core)
> Name     : L1D_PEND_MISS
> Equiv	 : None
> Flags    : None
> Desc     : Total number of outstanding L1 data cache misses at any cycle
> Code     : 0x48
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068725
> PMU name : core (Intel Core)
> Name     : L1D_SPLIT
> Equiv	 : None
> Flags    : None
> Desc     : Cache line split from L1 data cache
> Code     : 0x49
> Umask-00 : 0x01 : PMU : [LOADS] : None : Cache line split loads from the L1 data cache
> Umask-01 : 0x02 : PMU : [STORES] : None : Cache line split stores to the L1 data cache
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068726
> PMU name : core (Intel Core)
> Name     : SSE_PRE_MISS
> Equiv	 : None
> Flags    : None
> Desc     : Streaming SIMD Extensions (SSE) instructions missing all cache levels
> Code     : 0x4b
> Umask-00 : 0x00 : PMU : [NTA] : None : Streaming SIMD Extensions (SSE) Prefetch NTA instructions missing all cache levels
> Umask-01 : 0x01 : PMU : [L1] : None : Streaming SIMD Extensions (SSE) PrefetchT0 instructions missing all cache levels
> Umask-02 : 0x02 : PMU : [L2] : None : Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions missing all cache levels
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068727
> PMU name : core (Intel Core)
> Name     : LOAD_HIT_PRE
> Equiv	 : None
> Flags    : None
> Desc     : Load operations conflicting with a software prefetch to the same address
> Code     : 0x4c
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068728
> PMU name : core (Intel Core)
> Name     : L1D_PREFETCH
> Equiv	 : None
> Flags    : None
> Desc     : L1 data cache prefetch
> Code     : 0x4e
> Umask-00 : 0x10 : PMU : [REQUESTS] : [default] : L1 data cache prefetch requests
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068729
> PMU name : core (Intel Core)
> Name     : BUS_REQUEST_OUTSTANDING
> Equiv	 : None
> Flags    : None
> Desc     : Number of pending full cache line read transactions on the bus occurring in each cycle
> Code     : 0x60
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068730
> PMU name : core (Intel Core)
> Name     : BUS_BNR_DRV
> Equiv	 : None
> Flags    : None
> Desc     : Number of Bus Not Ready signals asserted
> Code     : 0x61
> Umask-00 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-01 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068731
> PMU name : core (Intel Core)
> Name     : BUS_DRDY_CLOCKS
> Equiv	 : None
> Flags    : None
> Desc     : Bus cycles when data is sent on the bus
> Code     : 0x62
> Umask-00 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-01 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068732
> PMU name : core (Intel Core)
> Name     : BUS_LOCK_CLOCKS
> Equiv	 : None
> Flags    : None
> Desc     : Bus cycles when a LOCK signal is asserted
> Code     : 0x63
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068733
> PMU name : core (Intel Core)
> Name     : BUS_DATA_RCV
> Equiv	 : None
> Flags    : None
> Desc     : Bus cycles while processor receives data
> Code     : 0x64
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068734
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_BRD
> Equiv	 : None
> Flags    : None
> Desc     : Burst read bus transactions
> Code     : 0x65
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068735
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_RFO
> Equiv	 : None
> Flags    : None
> Desc     : RFO bus transactions
> Code     : 0x66
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068736
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_WB
> Equiv	 : None
> Flags    : None
> Desc     : Explicit writeback bus transactions
> Code     : 0x67
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068737
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_IFETCH
> Equiv	 : None
> Flags    : None
> Desc     : Instruction-fetch bus transactions
> Code     : 0x68
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068738
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_INVAL
> Equiv	 : None
> Flags    : None
> Desc     : Invalidate bus transactions
> Code     : 0x69
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068739
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_PWR
> Equiv	 : None
> Flags    : None
> Desc     : Partial write bus transaction
> Code     : 0x6a
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068740
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_P
> Equiv	 : None
> Flags    : None
> Desc     : Partial bus transactions
> Code     : 0x6b
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068741
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_IO
> Equiv	 : None
> Flags    : None
> Desc     : IO bus transactions
> Code     : 0x6c
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068742
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_DEF
> Equiv	 : None
> Flags    : None
> Desc     : Deferred bus transactions
> Code     : 0x6d
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068743
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_BURST
> Equiv	 : None
> Flags    : None
> Desc     : Burst (full cache-line) bus transactions
> Code     : 0x6e
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068744
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_MEM
> Equiv	 : None
> Flags    : None
> Desc     : Memory bus transactions
> Code     : 0x6f
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068745
> PMU name : core (Intel Core)
> Name     : BUS_TRANS_ANY
> Equiv	 : None
> Flags    : None
> Desc     : All bus transactions
> Code     : 0x70
> Umask-00 : 0x40 : PMU : [SELF] : [default] : This core
> Umask-01 : 0xc0 : PMU : [BOTH_CORES] : None : Both cores
> Umask-02 : 0x00 : PMU : [THIS_AGENT] : [default] : This agent
> Umask-03 : 0x20 : PMU : [ALL_AGENTS] : None : Any agent on the bus
> Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
> Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
> Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean)
> Modif-03 : 0x03 : PMU : [i] : invert (boolean)
> Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
> #-----------------------------
> IDX	 : 23068746
> PMU name : core (Intel Core)
> Name     : EXT_SNOOP
> Equiv	 : None
> Flags    : None
> Desc     : External snoops responses
> Code     :...
 
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