Re: [perfmon2] core i7 uncore event count

[Qingyuan D. <dd...@gm...>]

Thank you! Yes, you are right, when I swap the addresses it seems works
well. But in Intel's manual 3B(Table B-5), it is that the 0x3B0 is for
MSR_UNCORE_PERFEVTSEL0 and the 0x3C0 is for MSR_UNCORE_PMC0. It's so
confusing and nearly made me bald after pulling hair for a whole day...
Thank you so much,
Qingyuan

On Fri, Oct 2, 2009 at 8:04 AM, stephane eranian <er...@go...>wrote:

> On Fri, Oct 2, 2009 at 2:33 AM, Qingyuan Deng <dd...@gm...> wrote:
> > Hi all,
> >
> > I am not sure if this topic is related to Perfmon2, but I think there
> should
> > be some more experienced people familiar with this...
> >
> > I am trying to manually program on uncore MSRs to count some events, by
> > adding some system calls into the kernel to read/write those MSR
> registers.
> >
> > The regular counting works(IA32_PERFEVTSELx and IA32_PMx), however, when
> I
> > tried to configure those uncore registers, it seems they do not count
> > anything, and the uncore_pmcs keep to be 0, whatever how I enable them.
> Here
> > is what I did:
> >
> > Suppose I want to use the uncore pmc 0 to count UNC_DRAM_OPEN.CH0(Umask:
> > 0x01, event number: 0x60)
> > I first set the first bit(EN_PC0) in MSR_UNCORE_PERF_GLOBAL_CTRL(address:
> > 0x391),  then I also set the EN bit in MSR_UNCORE_PERFEVTSEL0(address:
> > 0x3B0) to be 1, and specify the umask and event select fields, by set the
> > whole stuff to be 0x00400160. Then I assume this counter starts working,
> and
> > I run piece of code. After that, I read the value back from
> > MSR_UNCORE_PMC0(address: 0x3C0), but I got 0 from this counter.  And
> > actually I tried several uncore events and got all being 0. Did I miss
> > something or did I did it correctly?
> >
> I think you got the MSR address backwards.
>
> The config register MSR_UNCORE_PERFEVTSEL0 is 0x3c0
> The counter register MSR_UNCORE_PMC0 is 0x3b0.
>
> Note that uncore counters are 40 bits not 64-bit. So they can wraparound.
> To count beyond 40-bit you will need to install an interrupt vector +
> interrupt
> handler and select on which core, the uncore PMU will interrupt.
>