From: DJ D. <djd...@us...> - 2006-07-26 18:13:15
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Module Name: pcb Committed By: djdelorie Date: Wed Jul 26 18:13:15 UTC 2006 Modified Files: pcb/src: file.c Log Message: Enable loaded netlists by default. To generate a diff of this commit: cvs rdiff -r1.39 -r1.40 pcb/src/file.c To view the diffs online visit: http://cvs.sourceforge.net/viewcvs.py/pcb/pcb/src/file.c?r1=1.39&r2=1.40 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. |