From: Sheetal S. <she...@co...> - 2011-03-08 19:39:00
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This patch adds support for Qualcomm Scorpion and ScorpionMP CPU to Oprofile. Signed-off-by: Sheetal Sahasrabudhe <she...@co...> --- events/Makefile.am | 2 + events/arm/armv7-scorpion/events | 94 ++++++++++++++++++++++++++++++++ events/arm/armv7-scorpion/unit_masks | 4 ++ events/arm/armv7-scorpionmp/events | 77 ++++++++++++++++++++++++++ events/arm/armv7-scorpionmp/unit_masks | 4 ++ libop/op_cpu_type.c | 2 + libop/op_cpu_type.h | 2 + libop/op_events.c | 2 + utils/ophelp.c | 12 ++++ 9 files changed, 199 insertions(+), 0 deletions(-) create mode 100644 events/arm/armv7-scorpion/events create mode 100644 events/arm/armv7-scorpion/unit_masks create mode 100644 events/arm/armv7-scorpionmp/events create mode 100644 events/arm/armv7-scorpionmp/unit_masks diff --git a/events/Makefile.am b/events/Makefile.am index 475c4d3..60c4164 100644 --- a/events/Makefile.am +++ b/events/Makefile.am @@ -44,6 +44,8 @@ event_files = \ arm/armv6/events arm/armv6/unit_masks \ arm/armv7-common/events arm/armv7-common/unit_masks \ arm/armv7/events arm/armv7/unit_masks \ + arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ + arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ arm/mpcore/events arm/mpcore/unit_masks \ avr32/events avr32/unit_masks \ diff --git a/events/arm/armv7-scorpion/events b/events/arm/armv7-scorpion/events new file mode 100644 index 0000000..2925421 --- /dev/null +++ b/events/arm/armv7-scorpion/events @@ -0,0 +1,94 @@ +# ARM V7 events +# From Scorpion Processor Family Programmer's Reference Manual (PRM) +# +include:arm/armv7-common + +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU + +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle + +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier + +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_DUAL_CYCLE : Scorpion VIU dual cycle +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_SINGLE_CYCLE : Scorpion VIU single cycle +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAR_STALL_CYCLES : Scorpion VX pipe WAR cycles +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAW_STALL_CYCLES : Scorpion VX pipe WAW cycles +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_RAW_STALL_CYCLES : Scorpion VX pipe RAW cycles +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_LOAD_USE_STALL : Scorpion VX pipe load use stall +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAR_STALL_CYCLES : Scorpion VS pipe WAR stall cycles +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAW_STALL_CYCLES : Scorpion VS pipe WAW stall cycles +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_RAW_STALL_CYCLES : Scorpion VS pipe RAW stall cycles +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_INV_OPERATION : Scorpion invalid operation exceptions +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DIV_BY_ZERO : Scorpion divide by zero exceptions +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VX_PIPE : Scorpion conditional instruction fail VX pipe +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VS_PIPE : Scorpion conditional instruction fail VS pipe +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_OVERFLOW : Scorpion overflow exceptions +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_UNDERFLOW : Scorpion underflow exceptions +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DENORM : Scorpion denorm exceptions + +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses +event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits +event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses +event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits +event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses +event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits +event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses +event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits +event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses +event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits +event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses +event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus +event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus +event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes +event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus +event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) +event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus +event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) diff --git a/events/arm/armv7-scorpion/unit_masks b/events/arm/armv7-scorpion/unit_masks new file mode 100644 index 0000000..4027469 --- /dev/null +++ b/events/arm/armv7-scorpion/unit_masks @@ -0,0 +1,4 @@ +# ARM V7 PMNC possible unit masks +# +name:zero type:mandatory default:0x00 + 0x00 No unit mask diff --git a/events/arm/armv7-scorpionmp/events b/events/arm/armv7-scorpionmp/events new file mode 100644 index 0000000..ffd0691 --- /dev/null +++ b/events/arm/armv7-scorpionmp/events @@ -0,0 +1,77 @@ +# ARM V7 events +# From Scorpion Processor Family Programmer's Reference Manual (PRM) +# +include:arm/armv7-common + +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU + +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle + +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier + +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_DUAL_CYCLE : Scorpion VIU dual cycle +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_SINGLE_CYCLE : Scorpion VIU single cycle +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAR_STALL_CYCLES : Scorpion VX pipe WAR cycles +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAW_STALL_CYCLES : Scorpion VX pipe WAW cycles +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_RAW_STALL_CYCLES : Scorpion VX pipe RAW cycles +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_LOAD_USE_STALL : Scorpion VX pipe load use stall +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAR_STALL_CYCLES : Scorpion VS pipe WAR stall cycles +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAW_STALL_CYCLES : Scorpion VS pipe WAW stall cycles +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_RAW_STALL_CYCLES : Scorpion VS pipe RAW stall cycles +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_INV_OPERATION : Scorpion invalid operation exceptions +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DIV_BY_ZERO : Scorpion divide by zero exceptions +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VX_PIPE : Scorpion conditional instruction fail VX pipe +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VS_PIPE : Scorpion conditional instruction fail VS pipe +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_OVERFLOW : Scorpion overflow exceptions +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_UNDERFLOW : Scorpion underflow exceptions +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DENORM : Scorpion denorm exceptions + +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:SCORPIONMP_NUM_BARRIERS : Barriers +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:SCORPIONMP_BARRIER_CYCLES : Barrier cycles diff --git a/events/arm/armv7-scorpionmp/unit_masks b/events/arm/armv7-scorpionmp/unit_masks new file mode 100644 index 0000000..4027469 --- /dev/null +++ b/events/arm/armv7-scorpionmp/unit_masks @@ -0,0 +1,4 @@ +# ARM V7 PMNC possible unit masks +# +name:zero type:mandatory default:0x00 + 0x00 No unit mask diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c index ea3a530..b2ebf54 100644 --- a/libop/op_cpu_type.c +++ b/libop/op_cpu_type.c @@ -91,6 +91,8 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { { "AMD64 family14h", "x86-64/family14h", CPU_FAMILY14H, 4 }, { "AMD64 family15h", "x86-64/family15h", CPU_FAMILY15H, 6 }, { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 }, + { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 }, + { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 }, }; static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h index 381b3c7..9283ec7 100644 --- a/libop/op_cpu_type.h +++ b/libop/op_cpu_type.h @@ -88,6 +88,8 @@ typedef enum { CPU_FAMILY14H, /**< AMD family 14h */ CPU_FAMILY15H, /**< AMD family 15h */ CPU_WESTMERE, /* Intel Westmere microarchitecture */ + CPU_ARM_SCORPION, /**< ARM SCORPION */ + CPU_ARM_SCORPIONMP, /**< ARM SCORPIONMP */ MAX_CPU_TYPE } op_cpu; diff --git a/libop/op_events.c b/libop/op_events.c index 4546dda..30c3207 100644 --- a/libop/op_events.c +++ b/libop/op_events.c @@ -1013,6 +1013,8 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) case CPU_ARM_V7: case CPU_ARM_V7_CA9: case CPU_AVR32: + case CPU_ARM_SCORPION: + case CPU_ARM_SCORPIONMP: descr->name = "CPU_CYCLES"; break; diff --git a/utils/ophelp.c b/utils/ophelp.c index a87a640..ce8bace 100644 --- a/utils/ophelp.c +++ b/utils/ophelp.c @@ -552,6 +552,18 @@ int main(int argc, char const * argv[]) "Cortex A8 DDI (ARM DDI 0344B, revision r1p1)\n"; break; + case CPU_ARM_SCORPION: + event_doc = + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" + "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; + break; + + case CPU_ARM_SCORPIONMP: + event_doc = + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" + "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; + break; + case CPU_ARM_V7_CA9: event_doc = "See Cortex-A9 Technical Reference Manual\n" -- 1.7.4.1 -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum |
From: Maynard J. <may...@us...> - 2011-03-08 19:48:38
|
Sheetal Sahasrabudhe wrote: > This patch adds support for Qualcomm Scorpion and ScorpionMP CPU > to Oprofile. Please verify to us that 'make distcheck' passes with this patch applied. Thanks. -Maynard > > Signed-off-by: Sheetal Sahasrabudhe <she...@co...> > --- > events/Makefile.am | 2 + > events/arm/armv7-scorpion/events | 94 ++++++++++++++++++++++++++++++++ > events/arm/armv7-scorpion/unit_masks | 4 ++ > events/arm/armv7-scorpionmp/events | 77 ++++++++++++++++++++++++++ > events/arm/armv7-scorpionmp/unit_masks | 4 ++ > libop/op_cpu_type.c | 2 + > libop/op_cpu_type.h | 2 + > libop/op_events.c | 2 + > utils/ophelp.c | 12 ++++ > 9 files changed, 199 insertions(+), 0 deletions(-) > create mode 100644 events/arm/armv7-scorpion/events > create mode 100644 events/arm/armv7-scorpion/unit_masks > create mode 100644 events/arm/armv7-scorpionmp/events > create mode 100644 events/arm/armv7-scorpionmp/unit_masks > > diff --git a/events/Makefile.am b/events/Makefile.am > index 475c4d3..60c4164 100644 > --- a/events/Makefile.am > +++ b/events/Makefile.am > @@ -44,6 +44,8 @@ event_files = \ > arm/armv6/events arm/armv6/unit_masks \ > arm/armv7-common/events arm/armv7-common/unit_masks \ > arm/armv7/events arm/armv7/unit_masks \ > + arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ > + arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ > arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ > arm/mpcore/events arm/mpcore/unit_masks \ > avr32/events avr32/unit_masks \ > diff --git a/events/arm/armv7-scorpion/events b/events/arm/armv7-scorpion/events > new file mode 100644 > index 0000000..2925421 > --- /dev/null > +++ b/events/arm/armv7-scorpion/events > @@ -0,0 +1,94 @@ > +# ARM V7 events > +# From Scorpion Processor Family Programmer's Reference Manual (PRM) > +# > +include:arm/armv7-common > + > +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates > +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses > +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses > +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 > +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 > +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed > +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort > +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ > +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ > +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts > +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined > +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC > +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC > +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort > +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check > +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check > +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU > +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU > +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate > +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU > + > +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles > +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles > +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles > +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles > +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT > +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) > +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) > +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks > +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle > +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks > +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle > + > +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR > +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates > +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses > +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses > +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses > +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates > +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates > +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses > +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses > +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses > +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses > +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID > +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA > +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all > +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail > +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold > +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op > +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op > +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier > + > +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_DUAL_CYCLE : Scorpion VIU dual cycle > +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_SINGLE_CYCLE : Scorpion VIU single cycle > +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAR_STALL_CYCLES : Scorpion VX pipe WAR cycles > +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAW_STALL_CYCLES : Scorpion VX pipe WAW cycles > +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_RAW_STALL_CYCLES : Scorpion VX pipe RAW cycles > +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_LOAD_USE_STALL : Scorpion VX pipe load use stall > +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAR_STALL_CYCLES : Scorpion VS pipe WAR stall cycles > +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAW_STALL_CYCLES : Scorpion VS pipe WAW stall cycles > +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_RAW_STALL_CYCLES : Scorpion VS pipe RAW stall cycles > +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_INV_OPERATION : Scorpion invalid operation exceptions > +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DIV_BY_ZERO : Scorpion divide by zero exceptions > +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VX_PIPE : Scorpion conditional instruction fail VX pipe > +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VS_PIPE : Scorpion conditional instruction fail VS pipe > +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_OVERFLOW : Scorpion overflow exceptions > +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_UNDERFLOW : Scorpion underflow exceptions > +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DENORM : Scorpion denorm exceptions > + > +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits > +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses > +event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits > +event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses > +event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits > +event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses > +event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits > +event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses > +event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits > +event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses > +event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits > +event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses > +event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus > +event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus > +event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes > +event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus > +event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) > +event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus > +event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) > diff --git a/events/arm/armv7-scorpion/unit_masks b/events/arm/armv7-scorpion/unit_masks > new file mode 100644 > index 0000000..4027469 > --- /dev/null > +++ b/events/arm/armv7-scorpion/unit_masks > @@ -0,0 +1,4 @@ > +# ARM V7 PMNC possible unit masks > +# > +name:zero type:mandatory default:0x00 > + 0x00 No unit mask > diff --git a/events/arm/armv7-scorpionmp/events b/events/arm/armv7-scorpionmp/events > new file mode 100644 > index 0000000..ffd0691 > --- /dev/null > +++ b/events/arm/armv7-scorpionmp/events > @@ -0,0 +1,77 @@ > +# ARM V7 events > +# From Scorpion Processor Family Programmer's Reference Manual (PRM) > +# > +include:arm/armv7-common > + > +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates > +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses > +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses > +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 > +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 > +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed > +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort > +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ > +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ > +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts > +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined > +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC > +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC > +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort > +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check > +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check > +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU > +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU > +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate > +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU > + > +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles > +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles > +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles > +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles > +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT > +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) > +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) > +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks > +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle > +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks > +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle > + > +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR > +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates > +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses > +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses > +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses > +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates > +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates > +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses > +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses > +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses > +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses > +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID > +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA > +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all > +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail > +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold > +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op > +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op > +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier > + > +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_DUAL_CYCLE : Scorpion VIU dual cycle > +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_SINGLE_CYCLE : Scorpion VIU single cycle > +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAR_STALL_CYCLES : Scorpion VX pipe WAR cycles > +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAW_STALL_CYCLES : Scorpion VX pipe WAW cycles > +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_RAW_STALL_CYCLES : Scorpion VX pipe RAW cycles > +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_LOAD_USE_STALL : Scorpion VX pipe load use stall > +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAR_STALL_CYCLES : Scorpion VS pipe WAR stall cycles > +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAW_STALL_CYCLES : Scorpion VS pipe WAW stall cycles > +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_RAW_STALL_CYCLES : Scorpion VS pipe RAW stall cycles > +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_INV_OPERATION : Scorpion invalid operation exceptions > +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DIV_BY_ZERO : Scorpion divide by zero exceptions > +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VX_PIPE : Scorpion conditional instruction fail VX pipe > +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VS_PIPE : Scorpion conditional instruction fail VS pipe > +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_OVERFLOW : Scorpion overflow exceptions > +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_UNDERFLOW : Scorpion underflow exceptions > +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DENORM : Scorpion denorm exceptions > + > +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:SCORPIONMP_NUM_BARRIERS : Barriers > +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:SCORPIONMP_BARRIER_CYCLES : Barrier cycles > diff --git a/events/arm/armv7-scorpionmp/unit_masks b/events/arm/armv7-scorpionmp/unit_masks > new file mode 100644 > index 0000000..4027469 > --- /dev/null > +++ b/events/arm/armv7-scorpionmp/unit_masks > @@ -0,0 +1,4 @@ > +# ARM V7 PMNC possible unit masks > +# > +name:zero type:mandatory default:0x00 > + 0x00 No unit mask > diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c > index ea3a530..b2ebf54 100644 > --- a/libop/op_cpu_type.c > +++ b/libop/op_cpu_type.c > @@ -91,6 +91,8 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { > { "AMD64 family14h", "x86-64/family14h", CPU_FAMILY14H, 4 }, > { "AMD64 family15h", "x86-64/family15h", CPU_FAMILY15H, 6 }, > { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 }, > + { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 }, > + { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 }, > }; > > static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); > diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h > index 381b3c7..9283ec7 100644 > --- a/libop/op_cpu_type.h > +++ b/libop/op_cpu_type.h > @@ -88,6 +88,8 @@ typedef enum { > CPU_FAMILY14H, /**< AMD family 14h */ > CPU_FAMILY15H, /**< AMD family 15h */ > CPU_WESTMERE, /* Intel Westmere microarchitecture */ > + CPU_ARM_SCORPION, /**< ARM SCORPION */ > + CPU_ARM_SCORPIONMP, /**< ARM SCORPIONMP */ > MAX_CPU_TYPE > } op_cpu; > > diff --git a/libop/op_events.c b/libop/op_events.c > index 4546dda..30c3207 100644 > --- a/libop/op_events.c > +++ b/libop/op_events.c > @@ -1013,6 +1013,8 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) > case CPU_ARM_V7: > case CPU_ARM_V7_CA9: > case CPU_AVR32: > + case CPU_ARM_SCORPION: > + case CPU_ARM_SCORPIONMP: > descr->name = "CPU_CYCLES"; > break; > > diff --git a/utils/ophelp.c b/utils/ophelp.c > index a87a640..ce8bace 100644 > --- a/utils/ophelp.c > +++ b/utils/ophelp.c > @@ -552,6 +552,18 @@ int main(int argc, char const * argv[]) > "Cortex A8 DDI (ARM DDI 0344B, revision r1p1)\n"; > break; > > + case CPU_ARM_SCORPION: > + event_doc = > + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" > + "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; > + break; > + > + case CPU_ARM_SCORPIONMP: > + event_doc = > + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" > + "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; > + break; > + > case CPU_ARM_V7_CA9: > event_doc = > "See Cortex-A9 Technical Reference Manual\n" |
From: Sheetal S. <she...@co...> - 2011-03-08 21:22:13
|
Hi Maynard, On Tue, March 8, 2011 11:48 am, Maynard Johnson wrote: > Please verify to us that 'make distcheck' passes with this patch applied. 'make distcheck' succeeds with this patch applied but with GUI turned off. I turned off the GUI by setting DISTCHECK_CONFIGURE_FLAGS as follows in Makefile. DISTCHECK_CONFIGURE_FLAGS = --with-kernel-support --enable-gui=no If --enable-gui is left ON, then I get the following errors: make[5]: Entering directory `oprofile-0.9.7git/_build/gui/ui' o oprof_start.base.h ../../../gui/ui/oprof_start.base.ui make[5]: o: Command not found make[5]: [oprof_start.base.h] Error 127 (ignored) o oprof_start.base.cpp -impl oprof_start.base.h ../../../gui/ui/oprof_start.base.ui make[5]: o: Command not found make[5]: [oprof_start.base.cpp] Error 127 (ignored) g++ -DHAVE_CONFIG_H -I. -I../../../gui/ui -I../.. -W -Wall -fno-common -ftemplate-depth-50 -g -O2 -MT oprof_start.base.o -MD -MP -MF .deps/oprof_start.base.Tpo -c -o oprof_start.base.o oprof_start.base.cpp g++: oprof_start.base.cpp: No such file or directory g++: no input files make[5]: *** [oprof_start.base.o] Error 1 I didn't debug this further as it seemed to be completely unrelated to the patch. Since the patch does not touch any GUI code, I hope that is acceptable. Please let me know what you think. Thanks, Sheetal -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. |
From: Maynard J. <may...@us...> - 2011-03-09 15:48:37
|
On 03/08/2011 3:21 PM, Sheetal Sahasrabudhe wrote: > Hi Maynard, > > On Tue, March 8, 2011 11:48 am, Maynard Johnson wrote: >> Please verify to us that 'make distcheck' passes with this patch applied. > > 'make distcheck' succeeds with this patch applied but with GUI turned off. > I turned off the GUI by setting DISTCHECK_CONFIGURE_FLAGS as follows in Makefile. > DISTCHECK_CONFIGURE_FLAGS = --with-kernel-support --enable-gui=no > > If --enable-gui is left ON, then I get the following errors: > make[5]: Entering directory `oprofile-0.9.7git/_build/gui/ui' > o oprof_start.base.h ../../../gui/ui/oprof_start.base.ui > make[5]: o: Command not found > make[5]: [oprof_start.base.h] Error 127 (ignored) > o oprof_start.base.cpp -impl oprof_start.base.h ../../../gui/ui/oprof_start.base.ui > make[5]: o: Command not found > make[5]: [oprof_start.base.cpp] Error 127 (ignored) > g++ -DHAVE_CONFIG_H -I. -I../../../gui/ui -I../.. -W -Wall -fno-common -ftemplate-depth-50 -g -O2 -MT oprof_start.base.o -MD -MP -MF .deps/oprof_start.base.Tpo -c -o oprof_start.base.o oprof_start.base.cpp > g++: oprof_start.base.cpp: No such file or directory > g++: no input files > make[5]: *** [oprof_start.base.o] Error 1 > > > I didn't debug this further as it seemed to be completely unrelated to the patch. > Since the patch does not touch any GUI code, I hope that is acceptable. > Please let me know what you think. Right, your patch should have no impact on this. *Richard* (on cc) can review your patch without having a concern about that. I'm pretty sure the failure you see when you enable gui build is due to something Gert and I missed with the patch I committed on Feb 25 to enable oprofile gui parts to build with qt4. I tested the patch on a couple different distros, but apparently some circumstances can cause problems. *Gert*, any ideas off the top of your head? -Maynard > > Thanks, > Sheetal > |
From: Gert W. <gw....@gm...> - 2011-03-09 16:18:29
|
Am Mittwoch, den 09.03.2011, 09:48 -0600 schrieb Maynard Johnson: > On 03/08/2011 3:21 PM, Sheetal Sahasrabudhe wrote: > > Hi Maynard, > > > > On Tue, March 8, 2011 11:48 am, Maynard Johnson wrote: > >> Please verify to us that 'make distcheck' passes with this patch applied. > > > > 'make distcheck' succeeds with this patch applied but with GUI turned off. > > I turned off the GUI by setting DISTCHECK_CONFIGURE_FLAGS as follows in Makefile. > > DISTCHECK_CONFIGURE_FLAGS = --with-kernel-support --enable-gui=no > > > > If --enable-gui is left ON, then I get the following errors: > > make[5]: Entering directory `oprofile-0.9.7git/_build/gui/ui' > > o oprof_start.base.h ../../../gui/ui/oprof_start.base.ui > > make[5]: o: Command not found This means that configure didn't find the UI compiler but it also didn't complain about this. The config.log might be more helpful here. When you leave the GUI on by using the default then it will try to use QT3 and use the QT_DO_IT_ALL macro that I didn't touch. Apart from that: What distro do you use, does it have qt3 or qt4 and if the latter is the case, and did you try " DISTCHECK_CONFIGURE_FLAGS = --with-kernel-support --enable-gui=qt4 "? Hope that helps, Gert |
From: Maynard J. <may...@us...> - 2011-03-09 16:26:52
Attachments:
op-qt.patch
|
On 03/08/2011 3:21 PM, Sheetal Sahasrabudhe wrote: > Hi Maynard, > > On Tue, March 8, 2011 11:48 am, Maynard Johnson wrote: >> Please verify to us that 'make distcheck' passes with this patch applied. > > 'make distcheck' succeeds with this patch applied but with GUI turned off. > I turned off the GUI by setting DISTCHECK_CONFIGURE_FLAGS as follows in Makefile. > DISTCHECK_CONFIGURE_FLAGS = --with-kernel-support --enable-gui=no > > If --enable-gui is left ON, then I get the following errors: > make[5]: Entering directory `oprofile-0.9.7git/_build/gui/ui' > o oprof_start.base.h ../../../gui/ui/oprof_start.base.ui > make[5]: o: Command not found > make[5]: [oprof_start.base.h] Error 127 (ignored) > o oprof_start.base.cpp -impl oprof_start.base.h ../../../gui/ui/oprof_start.base.ui > make[5]: o: Command not found > make[5]: [oprof_start.base.cpp] Error 127 (ignored) > g++ -DHAVE_CONFIG_H -I. -I../../../gui/ui -I../.. -W -Wall -fno-common -ftemplate-depth-50 -g -O2 -MT oprof_start.base.o -MD -MP -MF .deps/oprof_start.base.Tpo -c -o oprof_start.base.o oprof_start.base.cpp > g++: oprof_start.base.cpp: No such file or directory > g++: no input files > make[5]: *** [oprof_start.base.o] Error 1 > > > I didn't debug this further as it seemed to be completely unrelated to the patch. > Since the patch does not touch any GUI code, I hope that is acceptable. > Please let me know what you think. Sheetal, please try the attached patch to fix the enable-gui problem. -Maynard > > Thanks, > Sheetal > |
From: Jean P. <jea...@ne...> - 2011-03-09 16:38:36
|
On Tue, Mar 8, 2011 at 8:03 PM, Sheetal Sahasrabudhe <she...@co...> wrote: > This patch adds support for Qualcomm Scorpion and ScorpionMP CPU > to Oprofile. > > Signed-off-by: Sheetal Sahasrabudhe <she...@co...> Code reviewed ok: Reviewed-by: Jean Pihet <j-...@ti...> Regards, Jean > --- > events/Makefile.am | 2 + > events/arm/armv7-scorpion/events | 94 ++++++++++++++++++++++++++++++++ > events/arm/armv7-scorpion/unit_masks | 4 ++ > events/arm/armv7-scorpionmp/events | 77 ++++++++++++++++++++++++++ > events/arm/armv7-scorpionmp/unit_masks | 4 ++ > libop/op_cpu_type.c | 2 + > libop/op_cpu_type.h | 2 + > libop/op_events.c | 2 + > utils/ophelp.c | 12 ++++ > 9 files changed, 199 insertions(+), 0 deletions(-) > create mode 100644 events/arm/armv7-scorpion/events > create mode 100644 events/arm/armv7-scorpion/unit_masks > create mode 100644 events/arm/armv7-scorpionmp/events > create mode 100644 events/arm/armv7-scorpionmp/unit_masks > > diff --git a/events/Makefile.am b/events/Makefile.am > index 475c4d3..60c4164 100644 > --- a/events/Makefile.am > +++ b/events/Makefile.am > @@ -44,6 +44,8 @@ event_files = \ > arm/armv6/events arm/armv6/unit_masks \ > arm/armv7-common/events arm/armv7-common/unit_masks \ > arm/armv7/events arm/armv7/unit_masks \ > + arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ > + arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ > arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ > arm/mpcore/events arm/mpcore/unit_masks \ > avr32/events avr32/unit_masks \ > diff --git a/events/arm/armv7-scorpion/events b/events/arm/armv7-scorpion/events > new file mode 100644 > index 0000000..2925421 > --- /dev/null > +++ b/events/arm/armv7-scorpion/events > @@ -0,0 +1,94 @@ > +# ARM V7 events > +# From Scorpion Processor Family Programmer's Reference Manual (PRM) > +# > +include:arm/armv7-common > + > +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates > +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses > +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses > +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 > +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 > +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed > +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort > +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ > +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ > +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts > +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined > +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC > +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC > +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort > +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check > +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check > +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU > +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU > +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate > +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU > + > +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles > +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles > +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles > +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles > +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT > +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) > +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) > +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks > +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle > +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks > +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle > + > +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR > +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates > +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses > +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses > +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses > +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates > +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates > +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses > +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses > +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses > +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses > +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID > +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA > +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all > +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail > +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold > +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op > +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op > +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier > + > +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_DUAL_CYCLE : Scorpion VIU dual cycle > +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_SINGLE_CYCLE : Scorpion VIU single cycle > +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAR_STALL_CYCLES : Scorpion VX pipe WAR cycles > +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAW_STALL_CYCLES : Scorpion VX pipe WAW cycles > +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_RAW_STALL_CYCLES : Scorpion VX pipe RAW cycles > +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_LOAD_USE_STALL : Scorpion VX pipe load use stall > +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAR_STALL_CYCLES : Scorpion VS pipe WAR stall cycles > +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAW_STALL_CYCLES : Scorpion VS pipe WAW stall cycles > +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_RAW_STALL_CYCLES : Scorpion VS pipe RAW stall cycles > +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_INV_OPERATION : Scorpion invalid operation exceptions > +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DIV_BY_ZERO : Scorpion divide by zero exceptions > +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VX_PIPE : Scorpion conditional instruction fail VX pipe > +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VS_PIPE : Scorpion conditional instruction fail VS pipe > +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_OVERFLOW : Scorpion overflow exceptions > +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_UNDERFLOW : Scorpion underflow exceptions > +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DENORM : Scorpion denorm exceptions > + > +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits > +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses > +event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits > +event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses > +event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits > +event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses > +event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits > +event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses > +event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits > +event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses > +event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits > +event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses > +event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus > +event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus > +event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes > +event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus > +event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) > +event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus > +event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) > diff --git a/events/arm/armv7-scorpion/unit_masks b/events/arm/armv7-scorpion/unit_masks > new file mode 100644 > index 0000000..4027469 > --- /dev/null > +++ b/events/arm/armv7-scorpion/unit_masks > @@ -0,0 +1,4 @@ > +# ARM V7 PMNC possible unit masks > +# > +name:zero type:mandatory default:0x00 > + 0x00 No unit mask > diff --git a/events/arm/armv7-scorpionmp/events b/events/arm/armv7-scorpionmp/events > new file mode 100644 > index 0000000..ffd0691 > --- /dev/null > +++ b/events/arm/armv7-scorpionmp/events > @@ -0,0 +1,77 @@ > +# ARM V7 events > +# From Scorpion Processor Family Programmer's Reference Manual (PRM) > +# > +include:arm/armv7-common > + > +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates > +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses > +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses > +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 > +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 > +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed > +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort > +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ > +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ > +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts > +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined > +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC > +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC > +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort > +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check > +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check > +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU > +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU > +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate > +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU > + > +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles > +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles > +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles > +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles > +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT > +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) > +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) > +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks > +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle > +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks > +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle > + > +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR > +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates > +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses > +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses > +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses > +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates > +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates > +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses > +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses > +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses > +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses > +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID > +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA > +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all > +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail > +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold > +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op > +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op > +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier > + > +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_DUAL_CYCLE : Scorpion VIU dual cycle > +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_SINGLE_CYCLE : Scorpion VIU single cycle > +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAR_STALL_CYCLES : Scorpion VX pipe WAR cycles > +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAW_STALL_CYCLES : Scorpion VX pipe WAW cycles > +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_RAW_STALL_CYCLES : Scorpion VX pipe RAW cycles > +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_LOAD_USE_STALL : Scorpion VX pipe load use stall > +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAR_STALL_CYCLES : Scorpion VS pipe WAR stall cycles > +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAW_STALL_CYCLES : Scorpion VS pipe WAW stall cycles > +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_RAW_STALL_CYCLES : Scorpion VS pipe RAW stall cycles > +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_INV_OPERATION : Scorpion invalid operation exceptions > +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DIV_BY_ZERO : Scorpion divide by zero exceptions > +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VX_PIPE : Scorpion conditional instruction fail VX pipe > +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VS_PIPE : Scorpion conditional instruction fail VS pipe > +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_OVERFLOW : Scorpion overflow exceptions > +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_UNDERFLOW : Scorpion underflow exceptions > +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DENORM : Scorpion denorm exceptions > + > +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:SCORPIONMP_NUM_BARRIERS : Barriers > +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:SCORPIONMP_BARRIER_CYCLES : Barrier cycles > diff --git a/events/arm/armv7-scorpionmp/unit_masks b/events/arm/armv7-scorpionmp/unit_masks > new file mode 100644 > index 0000000..4027469 > --- /dev/null > +++ b/events/arm/armv7-scorpionmp/unit_masks > @@ -0,0 +1,4 @@ > +# ARM V7 PMNC possible unit masks > +# > +name:zero type:mandatory default:0x00 > + 0x00 No unit mask > diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c > index ea3a530..b2ebf54 100644 > --- a/libop/op_cpu_type.c > +++ b/libop/op_cpu_type.c > @@ -91,6 +91,8 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { > { "AMD64 family14h", "x86-64/family14h", CPU_FAMILY14H, 4 }, > { "AMD64 family15h", "x86-64/family15h", CPU_FAMILY15H, 6 }, > { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 }, > + { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 }, > + { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 }, > }; > > static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); > diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h > index 381b3c7..9283ec7 100644 > --- a/libop/op_cpu_type.h > +++ b/libop/op_cpu_type.h > @@ -88,6 +88,8 @@ typedef enum { > CPU_FAMILY14H, /**< AMD family 14h */ > CPU_FAMILY15H, /**< AMD family 15h */ > CPU_WESTMERE, /* Intel Westmere microarchitecture */ > + CPU_ARM_SCORPION, /**< ARM SCORPION */ > + CPU_ARM_SCORPIONMP, /**< ARM SCORPIONMP */ > MAX_CPU_TYPE > } op_cpu; > > diff --git a/libop/op_events.c b/libop/op_events.c > index 4546dda..30c3207 100644 > --- a/libop/op_events.c > +++ b/libop/op_events.c > @@ -1013,6 +1013,8 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) > case CPU_ARM_V7: > case CPU_ARM_V7_CA9: > case CPU_AVR32: > + case CPU_ARM_SCORPION: > + case CPU_ARM_SCORPIONMP: > descr->name = "CPU_CYCLES"; > break; > > diff --git a/utils/ophelp.c b/utils/ophelp.c > index a87a640..ce8bace 100644 > --- a/utils/ophelp.c > +++ b/utils/ophelp.c > @@ -552,6 +552,18 @@ int main(int argc, char const * argv[]) > "Cortex A8 DDI (ARM DDI 0344B, revision r1p1)\n"; > break; > > + case CPU_ARM_SCORPION: > + event_doc = > + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" > + "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; > + break; > + > + case CPU_ARM_SCORPIONMP: > + event_doc = > + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" > + "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; > + break; > + > case CPU_ARM_V7_CA9: > event_doc = > "See Cortex-A9 Technical Reference Manual\n" > -- > 1.7.4.1 > > -- > Sent by an employee of the Qualcomm Innovation Center, Inc. > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum > > > ------------------------------------------------------------------------------ > What You Don't Know About Data Connectivity CAN Hurt You > This paper provides an overview of data connectivity, details > its effect on application quality, and explores various alternative > solutions. http://p.sf.net/sfu/progress-d2d > _______________________________________________ > oprofile-list mailing list > opr...@li... > https://lists.sourceforge.net/lists/listinfo/oprofile-list > |
From: Sheetal S. <she...@co...> - 2011-03-09 16:10:28
|
Hi Jean, On Wed, March 9, 2011 8:07 am, Jean Pihet wrote: > > Code reviewed ok: > Reviewed-by: Jean Pihet <j-...@ti...> Thanks for the code review. Regards, Sheetal -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. |
From: Sheetal S. <she...@co...> - 2011-03-09 17:06:13
|
Hi Maynard, On Wed, March 9, 2011 8:26 am, Maynard Johnson wrote: > Sheetal, please try the attached patch to fix the enable-gui problem. > > -Maynard I applied the patch that you sent and re-ran "make distcheck". This time it succeeded. Thanks, Sheetal -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. |
From: Maynard J. <may...@us...> - 2011-03-09 17:15:30
Attachments:
op-qt.patch
|
On 03/09/2011 11:05 AM, Sheetal Sahasrabudhe wrote: > Hi Maynard, > > On Wed, March 9, 2011 8:26 am, Maynard Johnson wrote: >> Sheetal, please try the attached patch to fix the enable-gui problem. >> >> -Maynard > > I applied the patch that you sent and re-ran "make distcheck". > This time it succeeded. Gert, sorry I neglected to cc you on the previous posting where I provided the patch to Sheetal. I've attached again here for convenience. Can you please review it and give it an ack if you concur with the fix? Thanks. -Maynard Signed-off-by: Maynard Johnson <ma...@us...> > > Thanks, > Sheetal > |
From: Gert W. <gw....@gm...> - 2011-03-09 18:06:13
|
Am Mittwoch, den 09.03.2011, 11:15 -0600 schrieb Maynard Johnson: > On 03/09/2011 11:05 AM, Sheetal Sahasrabudhe wrote: > > Hi Maynard, > > > > On Wed, March 9, 2011 8:26 am, Maynard Johnson wrote: > >> Sheetal, please try the attached patch to fix the enable-gui problem. > >> > >> -Maynard > > > > I applied the patch that you sent and re-ran "make distcheck". > > This time it succeeded. > Gert, sorry I neglected to cc you on the previous posting where I provided the > patch to Sheetal. I've attached again here for convenience. Can you please > review it and give it an ack if you concur with the fix? Thanks. Sorry, I don't think that's the proper way to fix it: Since QT_LIBS is usually an empty string at this point of the platform tests, and "test -n " tests whether the string is not empty, the QT_LIBS variable will not be set and the GUI will not be build. Therefore, the "make diskcheck" succeeds because make just doesn't see that UIC is not properly set. One could argue to use "test -z $QT_LIBS" to avoid overriding an environment variable that may point to the libraries, though. hope that helps, Gert |
From: Maynard J. <may...@us...> - 2011-03-09 21:25:19
Attachments:
op-qt.patch
|
On 03/09/2011 12:05 PM, Gert Wollny wrote: > Am Mittwoch, den 09.03.2011, 11:15 -0600 schrieb Maynard Johnson: >> On 03/09/2011 11:05 AM, Sheetal Sahasrabudhe wrote: >>> Hi Maynard, >>> >>> On Wed, March 9, 2011 8:26 am, Maynard Johnson wrote: >>>> Sheetal, please try the attached patch to fix the enable-gui problem. >>>> >>>> -Maynard >>> >>> I applied the patch that you sent and re-ran "make distcheck". >>> This time it succeeded. >> Gert, sorry I neglected to cc you on the previous posting where I provided the >> patch to Sheetal. I've attached again here for convenience. Can you please >> review it and give it an ack if you concur with the fix? Thanks. > > Sorry, I don't think that's the proper way to fix it: > Since QT_LIBS is usually an empty string at this point of the platform > tests, and "test -n " tests whether the string is not empty, the QT_LIBS > variable will not be set and the GUI will not be build. Therefore, the > "make diskcheck" succeeds because make just doesn't see that UIC is not > properly set. Yup, thanks for catching that bonehead mistake. I intended to check the QT_LIB (not QT_LIBS) variable that's set (or not) in the QT_DO_IT_ALL function. Correct patch is attached below. > > One could argue to use "test -z $QT_LIBS" to avoid overriding an > environment variable that may point to the libraries, though. > > hope that helps, > Gert > Signed-off-by: Maynard Johnson <may...@us...> |