p4 dropped overflow patch

[graydon h. <gr...@re...>]

hi,

here's a patch which corrects the "dropped overflows" I was seeing
occasionally on my p4 system. I also moved the lvtpc re-unmask up to the
top of the NMI handler, ostensibly to close a potential dropped nmi
window. I don't really know if that's significant though; it doesn't
solve the dropped events, but doesn't seem to hurt either. as near as I
can tell, the fault I was seeing was caused by this intel erratum (from
document 249678-012):

--snip--

Problem: Accessing a performance counter also enables the counter input
so that writing one half of the counter can cause the 
other half to increment. When a performance counter is written and the
event counter for the event being monitored is non-zero, 
the performance counter will be incremented by the value on that event
counter. Because the upper eight bits of the performance 
counter are not written at the same time as the lower 32 bits, the
increment due to the non-zero event counter may cause a carry 
to the upper bits such that the performance counter contains a value
higher than what was written. The worst-case error caused 
by this can be about 4 billion counts. 

Implication: When this erratum occurs, the performance counter will
contain a different value from that which was written. 

Workaround: If the performance counter is set to select a null event and
the CCCR for that counter has its compare bit set to zero, before the
performance counter is written, this erratum will not occur. 

--snip--

so, I simply reversed the order in which I update the registers after an
NMI: CCCR first and then counter. then the problem goes away.

ok to commit?

-graydon