[oprof-cvs] CVS: oprofile-www amd-events.php3,1.3,1.4 intel-events.php3,1.3,1.4

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Update of /cvsroot/oprofile/oprofile-www
In directory usw-pr-cvs1:/tmp/cvs-serv6106

Modified Files:
	amd-events.php3 intel-events.php3 
Log Message:
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Index: amd-events.php3
===================================================================
RCS file: /cvsroot/oprofile/oprofile-www/amd-events.php3,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4

--- amd-events.php3	6 Mar 2002 19:39:42 -0000	1.3
+++ amd-events.php3	6 Mar 2002 19:44:24 -0000	1.4
@@ -9,15 +9,15 @@
  
 <table class="eventtable">
 
-<tr class="tablehead"><td>Name</td><td>Description</td><td>Counters usable</td><td>CPU needed</td> <td>Unit mask options</td></tr>
+<tr class="tablehead"><td>Name</td><td>Description</td><td>Counters usable</td><td>Unit mask options</td></tr>
 
-</tr><tr><td>RETIRED_INSNS</td><td>	Retired instructions </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>RETIRED_OPS</td><td>	Retired Ops </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>ICACHE_FETCHES</td><td>	Instruction cache fetches) </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>ICACHE_MISSES</td><td>	Instruction cache misses) </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>DATA_CACHE_ACCESSES</td><td>	Data cache accesses </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>DATA_CACHE_MISSES</td><td>	Data cache misses </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>DATA_CACHE_REFILLS_FROM_L2</td><td>	Data cache refills from L2 </td><td> all</td><td> Athlon</td><td>
+</tr><tr><td>RETIRED_INSNS</td><td>	Retired instructions </td><td> all</td><td></td>
+</tr><tr><td>RETIRED_OPS</td><td>	Retired Ops </td><td> all</td><td></td>
+</tr><tr><td>ICACHE_FETCHES</td><td>	Instruction cache fetches) </td><td> all</td><td></td>
+</tr><tr><td>ICACHE_MISSES</td><td>	Instruction cache misses) </td><td> all</td><td></td>
+</tr><tr><td>DATA_CACHE_ACCESSES</td><td>	Data cache accesses </td><td> all</td><td></td>
+</tr><tr><td>DATA_CACHE_MISSES</td><td>	Data cache misses </td><td> all</td><td></td>
+</tr><tr><td>DATA_CACHE_REFILLS_FROM_L2</td><td>	Data cache refills from L2 </td><td> all</td><td>
 	10: (M)odified cache state
  <br/>
 	08: (O)wner cache state
@@ -34,7 +34,7 @@
 
 </tr>
 
-</tr><tr><td>DATA_CACHE_REFILLS_FROM_SYSTEM</td><td>	Data cache refills from system </td><td> all</td><td> Athlon</td><td>
+</tr><tr><td>DATA_CACHE_REFILLS_FROM_SYSTEM</td><td>	Data cache refills from system </td><td> all</td><td>
 	10: (M)odified cache state
  <br/>
 	08: (O)wner cache state
@@ -51,7 +51,7 @@
 
 </tr>
 
-</tr><tr><td>DATA_CACHE_WRITEBACKS</td><td>	Data cache write backs </td><td> all</td><td> Athlon</td><td>
+</tr><tr><td>DATA_CACHE_WRITEBACKS</td><td>	Data cache write backs </td><td> all</td><td>
 	10: (M)odified cache state
  <br/>
 	08: (O)wner cache state
@@ -68,18 +68,18 @@
 
 </tr>
 
-</tr><tr><td>RETIRED_BRANCHES</td><td>	Retired branches </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>RETIRED_BRANCHES_MISPREDICTED</td><td>	Retired branches mispredicted </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>RETIRED_TAKEN_BRANCHES</td><td>	Retired taken branches </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>RETIRED_TAKEN_BRANCHES_MISPREDICTED</td><td>	Retired taken branches mispredicted </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>L1_DTLB_MISSES_L2_DTLD_HITS</td><td>	L1 DTLB misses and L2 DTLB hits </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>L1_AND_L2_DTLB_MISSES</td><td>	L1 and L2 DTLB misses </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>MISALIGNED_DATA_REFS</td><td>	Misaligned data references </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>L1_ITLB_MISSES_L2_ITLB_HITS</td><td>	L1 ITLB misses </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>L1_AND_L2_ITLB_MISSES</td><td>	L1 and L2 ITLB misses </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>RETIRED_FAR_CONTROL_TRANSFERS</td><td>	Retired far control transfers </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>RETIRED_RESYNC_BRANCHES</td><td>	Retired resync branches </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>INTERRUPTS_MASKED</td><td>	Interrupts masked cycles </td><td> all</td><td> Athlon</td><td>
-</tr><tr><td>INTERRUPTS_MASKED_PENDING</td><td>	Interrupts masked while pending cycles </td><td> all</td><td> Athlon</td><td></tr>
+</tr><tr><td>RETIRED_BRANCHES</td><td>	Retired branches </td><td> all</td><td></td>
+</tr><tr><td>RETIRED_BRANCHES_MISPREDICTED</td><td>	Retired branches mispredicted </td><td> all</td><td></td>
+</tr><tr><td>RETIRED_TAKEN_BRANCHES</td><td>	Retired taken branches </td><td> all</td><td></td>
+</tr><tr><td>RETIRED_TAKEN_BRANCHES_MISPREDICTED</td><td>	Retired taken branches mispredicted </td><td> all</td><td></td>
+</tr><tr><td>L1_DTLB_MISSES_L2_DTLD_HITS</td><td>	L1 DTLB misses and L2 DTLB hits </td><td> all</td><td></td>
+</tr><tr><td>L1_AND_L2_DTLB_MISSES</td><td>	L1 and L2 DTLB misses </td><td> all</td><td></td>
+</tr><tr><td>MISALIGNED_DATA_REFS</td><td>	Misaligned data references </td><td> all</td><td></td>
+</tr><tr><td>L1_ITLB_MISSES_L2_ITLB_HITS</td><td>	L1 ITLB misses </td><td> all</td><td></td>
+</tr><tr><td>L1_AND_L2_ITLB_MISSES</td><td>	L1 and L2 ITLB misses </td><td> all</td><td></td>
+</tr><tr><td>RETIRED_FAR_CONTROL_TRANSFERS</td><td>	Retired far control transfers </td><td> all</td><td></td>
+</tr><tr><td>RETIRED_RESYNC_BRANCHES</td><td>	Retired resync branches </td><td> all</td><td></td>
+</tr><tr><td>INTERRUPTS_MASKED</td><td>	Interrupts masked cycles </td><td> all</td><td></td>
+</tr><tr><td>INTERRUPTS_MASKED_PENDING</td><td>	Interrupts masked while pending cycles </td><td> all</td><td></tr>
 </table>
 <?php require("end_page.php3"); end_page("amd-events.php3"); ?>

Index: intel-events.php3
===================================================================
RCS file: /cvsroot/oprofile/oprofile-www/intel-events.php3,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- intel-events.php3	6 Mar 2002 19:39:42 -0000	1.3
+++ intel-events.php3	6 Mar 2002 19:44:24 -0000	1.4
@@ -11,17 +11,17 @@
 
 <tr class="tablehead"><td>Name</td><td>Description</td><td>Counters usable</td><td>CPU needed</td> <td>Unit mask options</td></tr>
 
-<tr><td>CPU_CLK_UNHALTED</td><td>	clocks processor is not halted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>DATA_MEM_REFS</td><td>	all memory references, cachable and non </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>DCU_LINES_IN</td><td>	total lines allocated in the DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>DCU_M_LINES_IN</td><td>	number of M state lines allocated in DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>DCU_M_LINES_OUT</td><td>	number of M lines evicted from the DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>DCU_MISS_OUTSTANDING</td><td>	number of cycles while DCU miss outstanding </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>IFU_IFETCH</td><td>	number of non/cachable instruction fetches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>IFU_IFETCH_MISS</td><td>	number of instruction fetch misses </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>ITLB_MISS</td><td>	number of ITLB misses </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>IFU_MEM_STALL</td><td>	cycles instruction fetch pipe is stalled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>ILD_STALL</td><td>	cycles instruction length decoder is stalled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
+<tr><td>CPU_CLK_UNHALTED</td><td>	clocks processor is not halted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>DATA_MEM_REFS</td><td>	all memory references, cachable and non </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>DCU_LINES_IN</td><td>	total lines allocated in the DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>DCU_M_LINES_IN</td><td>	number of M state lines allocated in DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>DCU_M_LINES_OUT</td><td>	number of M lines evicted from the DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>DCU_MISS_OUTSTANDING</td><td>	number of cycles while DCU miss outstanding </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>IFU_IFETCH</td><td>	number of non/cachable instruction fetches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>IFU_IFETCH_MISS</td><td>	number of instruction fetch misses </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>ITLB_MISS</td><td>	number of ITLB misses </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>IFU_MEM_STALL</td><td>	cycles instruction fetch pipe is stalled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>ILD_STALL</td><td>	cycles instruction length decoder is stalled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
 </tr><tr><td>L2_IFETCH</td><td>	number of L2 instruction fetches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	08: (M)odified cache state
  <br/>
@@ -67,10 +67,10 @@
 
 </tr>
 
-</tr><tr><td>L2_LINES_IN</td><td>	number of allocated lines in L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>L2_LINES_OUT</td><td>	number of recovered lines from L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>L2_M_LINES_INM</td><td>	number of modified lines allocated in L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>L2_M_LINES_OUTM</td><td>	number of modified lines removed from L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
+</tr><tr><td>L2_LINES_IN</td><td>	number of allocated lines in L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>L2_LINES_OUT</td><td>	number of recovered lines from L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>L2_M_LINES_INM</td><td>	number of modified lines allocated in L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>L2_M_LINES_OUTM</td><td>	number of modified lines removed from L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
 </tr><tr><td>L2_RQSTS</td><td>	number of L2 requests </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	08: (M)odified cache state
  <br/>
@@ -86,9 +86,9 @@
 
 </tr>
 
-</tr><tr><td>L2_ADS</td><td>	number of L2 address strobes </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>L2_DBUS_BUSY</td><td>	number of cycles data bus was busy </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>L2_DMUS_BUSY_RD</td><td>	cycles data bus was busy in xfer from L2 to CPU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
+</tr><tr><td>L2_ADS</td><td>	number of L2 address strobes </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>L2_DBUS_BUSY</td><td>	number of cycles data bus was busy </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>L2_DMUS_BUSY_RD</td><td>	cycles data bus was busy in xfer from L2 to CPU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
 </tr><tr><td>BUS_DRDY_CLOCKS</td><td>	number of clocks DRDY is asserted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
  <br/>
@@ -107,7 +107,7 @@
 
 </tr>
 
-</tr><tr><td>BUS_REQ_OUTSTANDING</td><td>	number of outstanding bus requests </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
+</tr><tr><td>BUS_REQ_OUTSTANDING</td><td>	number of outstanding bus requests </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
 </tr><tr><td>BUS_TRAN_BRD</td><td>	number of burst read transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
  <br/>
@@ -216,20 +216,20 @@
 
 </tr>
 
-</tr><tr><td>BUS_DATA_RCV</td><td>	bus cycles this processor is receiving data </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>BUS_BNR_DRV</td><td>	bus cycles this processor is driving BNR pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>BUS_HIT_DRV</td><td>	bus cycles this processor is driving HIT pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>BUS_HITM_DRV</td><td>	bus cycles this processor is driving HITM pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>BUS_SNOOP_STALL</td><td>	cycles during bus snoop stall </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>COMP_FLOP_RET</td><td>	number of computational FP operations retired </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>FLOPS</td><td>	number of computational FP operations executed </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>FP_ASSIST</td><td>	number of FP exceptions handled by microcode </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>MUL</td><td>	number of multiplies </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>DIV</td><td>	number of divides </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>CYCLES_DIV_BUSY</td><td>	cycles divider is busy </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>LD_BLOCKS</td><td>	number of store buffer blocks </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>SB_DRAINS</td><td>	number of store buffer drain cycles </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-</tr><tr><td>MISALIGN_MEM_REF</td><td>	number of misaligned data memory references </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
+</tr><tr><td>BUS_DATA_RCV</td><td>	bus cycles this processor is receiving data </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>BUS_BNR_DRV</td><td>	bus cycles this processor is driving BNR pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>BUS_HIT_DRV</td><td>	bus cycles this processor is driving HIT pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>BUS_HITM_DRV</td><td>	bus cycles this processor is driving HITM pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>BUS_SNOOP_STALL</td><td>	cycles during bus snoop stall </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>COMP_FLOP_RET</td><td>	number of computational FP operations retired </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>FLOPS</td><td>	number of computational FP operations executed </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>FP_ASSIST</td><td>	number of FP exceptions handled by microcode </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>MUL</td><td>	number of multiplies </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>DIV</td><td>	number of divides </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>CYCLES_DIV_BUSY</td><td>	cycles divider is busy </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>LD_BLOCKS</td><td>	number of store buffer blocks </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>SB_DRAINS</td><td>	number of store buffer drain cycles </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+</tr><tr><td>MISALIGN_MEM_REF</td><td>	number of misaligned data memory references </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
 </tr><tr><td>EMON_KNI_PREF_DISPATCHED</td><td>	number of KNI pre-fetch/weakly ordered insns dispatched </td><td> all</td><td> PIII</td><td>
 	00: prefetch NTA
  <br/>
@@ -256,9 +256,9 @@
 
 </tr>
 
-<tr><td>INST_RETIRED</td><td>	number of instructions retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>UOPS_RETIRED</td><td>	number of UOPs retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>INST_DECODED</td><td>	number of instructions decoded </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
+<tr><td>INST_RETIRED</td><td>	number of instructions retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>UOPS_RETIRED</td><td>	number of UOPs retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>INST_DECODED</td><td>	number of instructions decoded </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
 <tr><td>EMON_KNI_INST_RETIRED</td><td>	number of KNI instructions retired </td><td> all</td><td> PIII</td><td>
 	00: packed and scalar
  <br/>
@@ -277,21 +277,21 @@
 
 </tr>
 
-<tr><td>HW_INT_RX</td><td>	number of hardware interrupts received </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>CYCLES_INT_MASKED</td><td>	cycles interrupts are disabled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>CYCLES_INT_PENDING_AND_MASKED</td><td>	cycles interrupts are disabled with pending interrupts </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>BR_INST_RETIRED</td><td>	number of branch instructions retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>BR_MISS_PRED_RETIRED</td><td>	number of mispredicted bracnhes retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>BR_TAKEN_RETIRED</td><td>	number of taken branches retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>BR_MISS_PRED_TAKEN_RET</td><td>	number of taken mispredictions branches retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>BR_INST_DECODED</td><td>	number of branch instructions decoded </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>BTB_MISSES</td><td>	number of branches that miss the BTB </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>BR_BOGUS</td><td>	number of bogus branches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>BACLEARS</td><td>	number of times BACLEAR is asserted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>RESOURCE_STALLS</td><td>	cycles during resource related stalls </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>PARTIAL_RAT_STALLS</td><td>	cycles or events for partial stalls </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>SEGMENT_REG_LOADS</td><td>	number of segment register loads </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
-<tr><td>MMX_SAT_INSTR_EXEC</td><td>	number of MMX saturating instructions executed </td><td> all</td><td> PII, PIII</td><td>
+<tr><td>HW_INT_RX</td><td>	number of hardware interrupts received </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>CYCLES_INT_MASKED</td><td>	cycles interrupts are disabled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>CYCLES_INT_PENDING_AND_MASKED</td><td>	cycles interrupts are disabled with pending interrupts </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>BR_INST_RETIRED</td><td>	number of branch instructions retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>BR_MISS_PRED_RETIRED</td><td>	number of mispredicted bracnhes retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>BR_TAKEN_RETIRED</td><td>	number of taken branches retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>BR_MISS_PRED_TAKEN_RET</td><td>	number of taken mispredictions branches retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>BR_INST_DECODED</td><td>	number of branch instructions decoded </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>BTB_MISSES</td><td>	number of branches that miss the BTB </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>BR_BOGUS</td><td>	number of bogus branches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>BACLEARS</td><td>	number of times BACLEAR is asserted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>RESOURCE_STALLS</td><td>	cycles during resource related stalls </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>PARTIAL_RAT_STALLS</td><td>	cycles or events for partial stalls </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>SEGMENT_REG_LOADS</td><td>	number of segment register loads </td><td> all</td><td> Pentium Pro, PII, PIII</td><td></td>
+<tr><td>MMX_SAT_INSTR_EXEC</td><td>	number of MMX saturating instructions executed </td><td> all</td><td> PII, PIII</td><td></td>
 <tr><td>MMX_UOPS_EXEC</td><td>	number of MMX UOPS executed </td><td> all</td><td> PII, PIII</td><td>
 	0f: mandatory
  <br/>
@@ -327,7 +327,7 @@
 
 </tr>
 
-<tr><td>MMX_ASSIST</td><td>	number of EMMS instructions executed </td><td> all</td><td> PII, PIII</td><td></tr>
+<tr><td>MMX_ASSIST</td><td>	number of EMMS instructions executed </td><td> all</td><td> PII, PIII</td><td></td></tr>
 </table> 
 
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