From: William C. <wc...@re...> - 2014-02-07 17:10:26
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Hi Will, Does the following revised patch address your comments on the future versions of the PMU on ARMv8? -Will On 02/04/2014 03:10 PM, William Cohen wrote: > The AArch64 support is provided as an ARM variant to allow use in both > 32-bit and 64-bit ARM environments. The support in this patch is just > the basic events described in the AArch64 documentation. AArch64 > processor implementation may provide additional implementation > specific events. One could add code to recognize those processor > specific implementations and include the armv8-common base events into > the event sets for the processor implementation specific events. > > Below is example run on the ARM Foundation simulator collecting data > on a build of OProfile. > > $ cd oprofile > $ operf make > ... > $ opreport -t 5 > Using /home/wcohen/oprofile/oprofile/oprofile_data/samples/ for samples directory. > > WARNING: Lost samples detected! See /home/wcohen/oprofile/oprofile/oprofile_data/samples/operf.log for details. > CPU: ARM AArch64 > Counted CPU_CYCLES events (Cycle) with a unit mask of 0x00 (No unit mask) count 100000 > CPU_CYCLES:100000| > samples| %| > ------------------ > 10943 90.5877 make > CPU_CYCLES:100000| > samples| %| > ------------------ > 5281 48.2592 make > 4543 41.5151 libc-2.17.so > 1079 9.8602 kallsyms > 40 0.3655 ld-2.17.so > 735 6.0844 sh > CPU_CYCLES:100000| > samples| %| > ------------------ > 321 43.6735 kallsyms > 298 40.5442 libc-2.17.so > 94 12.7891 bash > 22 2.9932 ld-2.17.so > > Signed-off-by: William Cohen <wc...@re...> > --- > events/Makefile.am | 1 + > events/arm/armv8-pmuv3/events | 38 ++++++++++++++++++++++++++++++++++++++ > events/arm/armv8-pmuv3/unit_masks | 4 ++++ > libop/op_cpu_type.c | 11 ++++++++++- > libop/op_cpu_type.h | 1 + > libop/op_events.c | 1 + > utils/opcontrol | 5 +++++ > utils/ophelp.c | 7 +++++++ > 8 files changed, 67 insertions(+), 1 deletion(-) > create mode 100644 events/arm/armv8-pmuv3/events > create mode 100644 events/arm/armv8-pmuv3/unit_masks > > diff --git a/events/Makefile.am b/events/Makefile.am > index ad45642..c17452e 100644 > --- a/events/Makefile.am > +++ b/events/Makefile.am > @@ -59,6 +59,7 @@ event_files = \ > arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ > arm/armv7-ca15/events arm/armv7-ca15/unit_masks \ > arm/mpcore/events arm/mpcore/unit_masks \ > + arm/armv8-pmuv3/events arm/armv8-pmuv3/unit_masks \ > avr32/events avr32/unit_masks \ > mips/20K/events mips/20K/unit_masks \ > mips/24K/events mips/24K/unit_masks \ > diff --git a/events/arm/armv8-pmuv3/events b/events/arm/armv8-pmuv3/events > new file mode 100644 > index 0000000..3cdff03 > --- /dev/null > +++ b/events/arm/armv8-pmuv3/events > @@ -0,0 +1,38 @@ > +# > +# Copyright (c) Red Hat, 2014. > +# Contributed by William Cohen <wc...@re...> > +# > +# ARMv8 pmu v3 architected events > + > +event:0x00 um:zero minimum:500 name:SW_INCR : Instruction architecturally executed, condition code check pass, software increment > +event:0x01 um:zero minimum:5000 name:L1I_CACHE_REFILL : Level 1 instruction cache refill > +event:0x02 um:zero minimum:5000 name:L1I_TLB_REFILL : Level 1 instruction TLB refill > +event:0x03 um:zero minimum:5000 name:L1D_CACHE_REFILL : Level 1 data cache refill > +event:0x04 um:zero minimum:5000 name:L1D_CACHE : Level 1 data cache access > +event:0x05 um:zero minimum:5000 name:L1D_TLB_REFILL : Level 1 data TLB refill > +event:0x06 um:zero minimum:100000 name:LD_RETIRED : Instruction architecturally executed, condition code check pass, load > +event:0x07 um:zero minimum:100000 name:ST_RETIRED : Instruction architecturally executed, condition code check pass, store > +event:0x08 um:zero minimum:100000 name:INST_RETIRED : Instruction architecturally executed > +event:0x09 um:zero minimum:500 name:EXC_TAKEN : Exception taken > +event:0x0A um:zero minimum:500 name:EXC_RETURN : Instruction architecturally executed, condition code check pass, exception return > +event:0x0B um:zero minimum:500 name:CID_WRITE_RETIRED : Instruction architecturally executed, condition code check pass, write to CONTEXTIDR > +event:0x0C um:zero minimum:5000 name:PC_WRITE_RETIRED : Instruction architecturally executed, condition code check pass, software change of the PC > +event:0x0D um:zero minimum:5000 name:BR_IMMED_RETIRED : Instruction architecturally executed, immediate branch > +event:0x0E um:zero minimum:5000 name:BR_RETURN_RETIRED : Instruction architecturally executed, condition code check pass, procedure return > +event:0x0F um:zero minimum:500 name:UNALIGNED_LDST_RETIRED : Instruction architecturally executed, condition code check pass, unaligned load or store > +event:0x10 um:zero minimum:5000 name:BR_MIS_PRED : Mispredicted or not predicted branch speculatively executed > +event:0x11 um:zero minimum:100000 name:CPU_CYCLES : Cycle > +event:0x12 um:zero minimum:5000 name:BR_PRED : Predictable branch speculatively executed > +event:0x13 um:zero minimum:100000 name:MEM_ACCESS : Data memory access > +event:0x14 um:zero minimum:5000 name:L1I_CACHE : Level 1 instruction cache access > +event:0x15 um:zero minimum:5000 name:L1D_CACHE_WB : Level 1 data cache write-back > +event:0x16 um:zero minimum:5000 name:L2D_CACHE : Level 2 data cache access > +event:0x17 um:zero minimum:5000 name:L2D_CACHE_REFILL : Level 2 data cache refill > +event:0x18 um:zero minimum:5000 name:L2D_CACHE_WB : Level 2 data cache write-back > +event:0x19 um:zero minimum:5000 name:BUS_ACCESS : Bus access > +event:0x1A um:zero minimum:500 name:MEMORY_ERROR : Local memory error > +event:0x1B um:zero minimum:100000 name:INST_SPEC : Operation speculatively executed > +event:0x1C um:zero minimum:5000 name:TTBR_WRITE_RETIRED : Instruction architecturally executed, condition code check pass, write to TTBR > +event:0x1D um:zero minimum:5000 name:BUS_CYCLES : Bus cycle > +event:0x1F um:zero minimum:5000 name:L1D_CACHE_ALLOCATE : Level 1 data cache allocation without refill > +event:0x20 um:zero minimum:5000 name:L2D_CACHE_ALLOCATE : Level 2 data cache allocation without refill > diff --git a/events/arm/armv8-pmuv3/unit_masks b/events/arm/armv8-pmuv3/unit_masks > new file mode 100644 > index 0000000..7666c35 > --- /dev/null > +++ b/events/arm/armv8-pmuv3/unit_masks > @@ -0,0 +1,4 @@ > +# ARMv8 architected events unit masks > +# > +name:zero type:mandatory default:0x00 > + 0x00 No unit mask > diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c > index 1ae2913..396b35d 100644 > --- a/libop/op_cpu_type.c > +++ b/libop/op_cpu_type.c > @@ -129,6 +129,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { > { "e6500", "ppc/e6500", CPU_PPC_E6500, 6 }, > { "Intel Silvermont microarchitecture", "i386/silvermont", CPU_SILVERMONT, 2 }, > { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, > + { "ARM AArch64", "arm/armv8-pmuv3", CPU_ARM_V8_PMUV3, 6 }, > }; > > static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); > @@ -394,6 +395,13 @@ static op_cpu _get_arm_cpu_type(void) > return op_get_cpu_number("arm/armv7-ca9"); > case 0xc0f: > return op_get_cpu_number("arm/armv7-ca15"); > + case 0xd00: > + return op_get_cpu_number("arm/armv8-pmuv3"); > + } > + } else if (vendorid == 0x50) { /* Applied Micro Circuits Corpation */ > + switch (cpuid) { > + case 0x000: > + return op_get_cpu_number("arm/armv8-pmuv3"); > } > } else if (vendorid == 0x69) { /* Intel xscale */ > switch (cpuid >> 9) { > @@ -631,7 +639,8 @@ static op_cpu __get_cpu_type_alt_method(void) > (strncmp(uname_info.machine, "ppc64le", 7) == 0)) { > return _get_ppc64_cpu_type(); > } > - if (strncmp(uname_info.machine, "arm", 3) == 0) { > + if (strncmp(uname_info.machine, "arm", 3) == 0 || > + strncmp(uname_info.machine, "aarch64", 7) == 0) { > return _get_arm_cpu_type(); > } > if (strncmp(uname_info.machine, "tile", 4) == 0) { > diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h > index 67e16de..733fb26 100644 > --- a/libop/op_cpu_type.h > +++ b/libop/op_cpu_type.h > @@ -109,6 +109,7 @@ typedef enum { > CPU_PPC_E6500, /**< e6500 */ > CPU_SILVERMONT, /** < Intel Silvermont microarchitecture */ > CPU_ARM_KRAIT, /**< ARM KRAIT */ > + CPU_ARM_V8_PMUV3, /* ARM V8 base architected events */ > MAX_CPU_TYPE > } op_cpu; > > diff --git a/libop/op_events.c b/libop/op_events.c > index 358a154..ee9001b 100644 > --- a/libop/op_events.c > +++ b/libop/op_events.c > @@ -1253,6 +1253,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) > case CPU_ARM_SCORPION: > case CPU_ARM_SCORPIONMP: > case CPU_ARM_KRAIT: > + case CPU_ARM_V8_PMUV3: > descr->name = "CPU_CYCLES"; > break; > > diff --git a/utils/opcontrol b/utils/opcontrol > index 38bb1ac..04a4a91 100755 > --- a/utils/opcontrol > +++ b/utils/opcontrol > @@ -400,6 +400,11 @@ do_init() > do_deinit > exit 1 > ;; > + aarch64/*) > + echo "*** ARM AArch64 processors are not supported with opcontrol. Please use operf instead. ***" > + do_deinit > + exit 1 > + ;; > esac > fi > > diff --git a/utils/ophelp.c b/utils/ophelp.c > index af4c1e5..ad42884 100644 > --- a/utils/ophelp.c > +++ b/utils/ophelp.c > @@ -656,6 +656,13 @@ int main(int argc, char const * argv[]) > "Cortex A15 DDI (ARM DDI 0438F, revision r3p1)\n"; > break; > > + case CPU_ARM_V8_PMUV3: > + event_doc = > + "See ARM Architecture Reference Manual \n" > + "ARMv8, for ARMv8-A architecture profile\n" > + "DDI (ARM DDI0487A.a)\n"; > + break; > + > case CPU_PPC64_PA6T: > event_doc = > "See PA6T Power Implementation Features Book IV\n" > |