From: Andi K. <an...@fi...> - 2013-06-18 23:40:50
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From: Suravee Suthikulpanit <sur...@am...> In the new unit mask parsing scheme, "extra:" should always followed by named mask. This patch fixes the entries which does not follow the scheme. Signed-off-by: Suravee Suthikulpanit <sur...@am...> --- events/i386/core_2/unit_masks | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/events/i386/core_2/unit_masks b/events/i386/core_2/unit_masks index f1d64eb..6bc0960 100644 --- a/events/i386/core_2/unit_masks +++ b/events/i386/core_2/unit_masks @@ -33,7 +33,7 @@ name:sse_prefetch type:exclusive default:0x0 0x00 prefetch NTA instructions executed. 0x01 prefetch T1 instructions executed. 0x02 prefetch T1 and T2 instructions executed. - 0x03 extra: SSE weakly-ordered stores + 0x03 SSE weakly-ordered stores name:simd_instr_type_exec type:bitmask default:0x3f 0x01 SIMD packed multiplies 0x02 SIMD packed shifts @@ -41,7 +41,7 @@ name:simd_instr_type_exec type:bitmask default:0x3f 0x08 SIMD unpack operations 0x10 SIMD packed logical 0x20 SIMD packed arithmetic - 0x3f extra: all of the above + 0x3f all of the above name:mmx_trans type:bitmask default:0x3 0x01 float->MMX transitions 0x02 MMX->float transitions @@ -138,8 +138,8 @@ name:inst_retired type:bitmask default:0x00 0x02 extra: Stores 0x04 extra: Other name:x87_ops_retired type:exclusive default:0xfe - 0x01 extra: FXCH instructions retired - 0xfe extra: Retired floating-point computational operations (precise) + 0x01 FXCH instructions retired + 0xfe Retired floating-point computational operations (precise) name:uops_retired type:bitmask default:0x0f 0x01 Fused load+op or load+indirect branch retired 0x02 Fused store address + data retired -- 1.8.1.4 |