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[oprof-cvs] CVS: oprofile/events/x86-64/family10 events, 1.4, 1.5 unit_masks, 1.3, 1.4
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From: Maynard J. <may...@us...> - 2009-04-17 18:43:55
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Update of /cvsroot/oprofile/oprofile/events/x86-64/family10 In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv4205/events/x86-64/family10 Modified Files: events unit_masks Log Message: Add IBS support, patch 2 of 4 Index: events =================================================================== RCS file: /cvsroot/oprofile/oprofile/events/x86-64/family10/events,v retrieving revision 1.4 retrieving revision 1.5 diff -u -p -d -r1.4 -r1.5 --- events 24 Nov 2008 16:39:31 -0000 1.4 +++ events 17 Apr 2009 18:43:42 -0000 1.5 @@ -1,4 +1,3 @@ -# # AMD Family 10 processor performance events # # Copyright OProfile authors @@ -8,12 +7,17 @@ # Suravee Suthikulpanit <suravee.suthikulpanit at amd.com> # # Sources: BIOS and Kernel Developer's Guide for AMD Family 10h Processors, -# Publication# 31116, Revision 3.00, 7 September 2007 +# Publication# 31116, Revision 3.20, February 04, 2009 # # Software Optimization Guide for AMD Family 10h Processors, # Publication# 40546, Revision 3.04, September 2007 # -# This file was last updated on 11 January 2008. +# Revision: 1.1 +# +# ChangeLog: 06 April 2009. +# - Add IBS-derived events +# - Update from BKDG Rev 3.00 to Rev 3.20 +# - Add Events 165h, 1c0h, 1cfh, 1d3h-1d5h # # Floating point events event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops @@ -59,10 +63,11 @@ event:0x65 counters:0,1,2,3 um:memreqtyp event:0x67 counters:0,1,2,3 um:dataprefetch minimum:500 name:DATA_PREFETCHES : Data prefetcher event:0x6c counters:0,1,2,3 um:systemreadresponse minimum:500 name:NORTHBRIDGE_READ_RESPONSES : Northbridge read responses by coherency state event:0x6d counters:0,1,2,3 um:octword_transfer minimum:500 name:OCTWORD_WRITE_TRANSFERS : Octwords written to system -event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state +event:0x76 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state event:0x7d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 Cache event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback +event:0x165 counters:0,1,2,3 um:page_size_mismatches minimum:500 name:PAGE_SIZE_MISMATCHES : Page Size Mismatches # Instruction Cache events event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches (RevE) @@ -81,7 +86,7 @@ event:0x99 counters:0,1,2,3 um:zero mini event:0x9a counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS_ABORTED : The number of ITLB reloads aborted # Execution Unit events -event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs) +event:0xc0 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs) event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts) event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired mispredicted branch instructions @@ -96,7 +101,7 @@ event:0xcb counters:0,1,2,3 um:fpu_instr event:0xcc counters:0,1,2,3 um:fpu_fastpath minimum:500 name:RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS : Retired FastPath double-op instructions event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0) event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending -event:0xcf counters:0,1,2,3 um:zero minimum:10 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts +event:0xcf counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts event:0xd0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Nothing to dispatch (decoder empty) event:0xd1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch stalls event:0xd2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_BRANCH_ABORT : Dispatch stall from branch abort to retire @@ -108,11 +113,16 @@ event:0xd7 counters:0,1,2,3 um:zero mini event:0xd8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_LS_FULL : Dispatch stall when LS is full event:0xd9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_WAITING_FOR_ALL_QUIET : Dispatch stall when waiting for all to be quiet event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch Stall for Far Transfer or Resync to Retire -event:0xdb counters:0,1,2,3 um:fpu_exceptions minimum:1 name:FPU_EXCEPTIONS : FPU exceptions -event:0xdc counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : The number of matches on the address in breakpoint register DR0 -event:0xdd counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : The number of matches on the address in breakpoint register DR1 -event:0xde counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : The number of matches on the address in breakpoint register DR2 -event:0xdf counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : The number of matches on the address in breakpoint register DR3 +event:0xdb counters:0,1,2,3 um:fpu_exceptions minimum:500 name:FPU_EXCEPTIONS : FPU exceptions +event:0xdc counters:0,1,2,3 um:zero minimum:500 name:DR0_BREAKPOINTS : The number of matches on the address in breakpoint register DR0 +event:0xdd counters:0,1,2,3 um:zero minimum:500 name:DR1_BREAKPOINTS : The number of matches on the address in breakpoint register DR1 +event:0xde counters:0,1,2,3 um:zero minimum:500 name:DR2_BREAKPOINTS : The number of matches on the address in breakpoint register DR2 +event:0xdf counters:0,1,2,3 um:zero minimum:500 name:DR3_BREAKPOINTS : The number of matches on the address in breakpoint register DR3 +event:0x1c0 counters:0,1,2,3 um:retired_x87_fp minimum:500 name:RETIRED_X87_FLOATING_POINT_OPERATIONS : Retired x87 Floating Point Operations (RevC and later) +event:0x1cf counters:0,1,2,3 um:zero minimum:50000 name:IBS_OPS_TAGGED : IBS Ops Tagged (RevC and later) +event:0x1d3 counters:0,1,2,3 um:zero minimum:500 name:LFENCE_INSTRUCTIONS_RETIRED : LFENCE Instructions Retired (RevC and later) +event:0x1d4 counters:0,1,2,3 um:zero minimum:500 name:SFENCE_INSTRUCTIONS_RETIRED : SFENCE Instructions Retired (RevC and later) +event:0x1d5 counters:0,1,2,3 um:zero minimum:500 name:MFENCE_INSTRUCTIONS_RETIRED : MFENCE Instructions Retired (RevC and later) # Memory Controler events event:0xe0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM accesses @@ -149,3 +159,72 @@ event:0x4e0 counters:0,1,2,3 um:l3_cache event:0x4e1 counters:0,1,2,3 um:l3_cache minimum:500 name:L3_CACHE_MISSES : Number of L3 cache misses from each core event:0x4e2 counters:0,1,2,3 um:l3_fill minimum:500 name:L3_FILLS_CAUSED_BY_L2_EVICTIONS : Number of L3 fills caused by L2 evictions per core event:0x4e3 counters:0,1,2,3 um:l3_evict minimum:500 name:L3_EVICTIONS : Number of L3 cache line evictions by cache state + +############################### +# IBS FETCH EVENTS +############################### +event:0xf000 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ALL : All IBS fetch samples +event:0xf001 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_KILLED : IBS fetch killed +event:0xf002 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ATTEMPTED : IBS fetch attempted +event:0xf003 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_COMPLETED : IBS fetch completed +event:0xf004 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ABORTED : IBS fetch aborted +event:0xf005 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ITLB_HITS : IBS ITLB hit +event:0xf006 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_HITS : IBS L1 ITLB misses (and L2 ITLB hits) +event:0xf007 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_MISSES : IBS L1 L2 ITLB miss +event:0xf008 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ICACHE_MISSES : IBS Instruction cache misses +event:0xf009 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ICACHE_HITS : IBS Instruction cache hit +event:0xf00A ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_4K_PAGE : IBS 4K page translation +event:0xf00B ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_2M_PAGE : IBS 2M page translation +# +event:0xf00E ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_LATENCY : IBS fetch latency + +############################### +# IBS OP EVENTS +############################### +event:0xf100 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_ALL : All IBS op samples +event:0xf101 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_TAG_TO_RETIRE : IBS tag-to-retire cycles +event:0xf102 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_COMP_TO_RET : IBS completion-to-retire cycles +event:0xf103 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_BRANCH_RETIRED : IBS branch op +event:0xf104 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MISPREDICTED_BRANCH : IBS mispredicted branch op +event:0xf105 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_TAKEN_BRANCH : IBS taken branch op +event:0xf106 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MISPREDICTED_BRANCH_TAKEN : IBS mispredicted taken branch op +event:0xf107 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_RETURNS : IBS return op +event:0xf108 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MISPREDICTED_RETURNS : IBS mispredicted return op +event:0xf109 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_RESYNC : IBS resync op +event:0xf200 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_ALL_LOAD_STORE : IBS all load store ops +event:0xf201 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_LOAD : IBS load ops +event:0xf202 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_STORE : IBS store ops +event:0xf203 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_HITS : IBS L1 DTLB hit +event:0xf204 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_MISS_L2_DTLB_HIT : IBS L1 DTLB misses L2 hits +event:0xf205 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_L2_DTLB_MISS : IBS L1 and L2 DTLB misses +event:0xf206 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DATA_CACHE_MISS : IBS data cache misses +event:0xf207 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DATA_HITS : IBS data cache hits +event:0xf208 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MISALIGNED_DATA_ACC : IBS misaligned data access +event:0xf209 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_BANK_CONF_LOAD : IBS bank conflict on load op +event:0xf20A ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_BANK_CONF_STORE : IBS bank conflict on store op +event:0xf20B ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_FORWARD : IBS store-to-load forwarded +event:0xf20C ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_CANCELLED : IBS store-to-load cancelled +event:0xf20D ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DCUC_MEM_ACC : IBS UC memory access +event:0xf20E ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DCWC_MEM_ACC : IBS WC memory access +event:0xf20F ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_LOCKED : IBS locked operation +event:0xf210 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MAB_HIT : IBS MAB hit +event:0xf211 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_4K : IBS L1 DTLB 4K page +event:0xf212 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_2M : IBS L1 DTLB 2M page +event:0xf213 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_1G : IBS L1 DTLB 1G page +event:0xf215 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L2_DTLB_4K : IBS L2 DTLB 4K page +event:0xf216 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L2_DTLB_2M : IBS L2 DTLB 2M page +event:0xf217 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L2_DTLB_1G : IBS L2 DTLB 1G page +event:0xf219 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DC_LOAD_LAT : IBS data cache miss load latency +event:0xf240 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_ONLY : IBS northbridge local +event:0xf241 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_ONLY : IBS northbridge remote +event:0xf242 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_L3 : IBS northbridge local L3 +event:0xf243 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_CACHE : IBS northbridge local core L1 or L2 cache +event:0xf244 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_CACHE : IBS northbridge local core L1, L2, L3 cache +event:0xf245 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_DRAM : IBS northbridge local DRAM +event:0xf246 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_DRAM : IBS northbridge remote DRAM +event:0xf247 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_OTHER : IBS northbridge local APIC MMIO Config PCI +event:0xf248 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_OTHER : IBS northbridge remote APIC MMIO Config PCI +event:0xf249 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_CACHE_MODIFIED : IBS northbridge cache modified state +event:0xf24A ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_CACHE_OWNED : IBS northbridge cache owned state +event:0xf24B ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_CACHE_LAT : IBS northbridge local cache latency +event:0xf24C ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_CACHE_LAT : IBS northbridge remote cache latency Index: unit_masks =================================================================== RCS file: /cvsroot/oprofile/oprofile/events/x86-64/family10/unit_masks,v retrieving revision 1.3 retrieving revision 1.4 diff -u -p -d -r1.3 -r1.4 --- unit_masks 21 May 2008 00:31:07 -0000 1.3 +++ unit_masks 17 Apr 2009 18:43:42 -0000 1.4 @@ -3,17 +3,22 @@ # # Copyright OProfile authors # Copyright (c) 2006-2008 Advanced Micro Devices -# Contributed by Ray Bryant <raybry at amd.com> +# Contributed by Ray Bryant <raybry at amd.com>, # Jason Yeh <jason.yeh at amd.com> # Suravee Suthikulpanit <suravee.suthikulpanit at amd.com> # # Sources: BIOS and Kernel Developer's Guide for AMD Family 10h Processors, -# Publication# 31116, Revision 3.00, September 7, 2007 +# Publication# 31116, Revision 3.20, February 04, 2009 # # Software Optimization Guide for AMD Family 10h Processors, # Publication# 40546, Revision 3.04, September 2007 # -# This file was last updated on 11 January 2008. +# Revision: 1.1 +# +# ChangeLog: 06 April 2009. +# - Add IBS-derived events +# - Update from BKDG Rev 3.00 to Rev 3.20 +# - Add Events 165h, 1c0h, 1cfh, 1d3h-1d5h # name:zero type:mandatory default:0x0 0x0 No unit mask @@ -50,7 +55,7 @@ name:segregload type:bitmask default:0x7 name:fpu_instr type:bitmask default:0x07 0x01 x87 instructions 0x02 MMX & 3DNow instructions - 0x04 SSE & SSE2 instructions + 0x04 SSE instructions (SSE, SSE2, SSE3, and SSE4A) name:fpu_fastpath type:bitmask default:0x07 0x01 With low op in position 0 0x02 With low op in position 1 @@ -60,15 +65,13 @@ name:fpu_exceptions type:bitmask default 0x02 SSE retype microfaults 0x04 SSE reclass microfaults 0x08 SSE and x87 microtraps -name:page_access type:bitmask default:0xff +name:page_access type:bitmask default:0x3f 0x01 DCT0 Page hit 0x02 DCT0 Page miss 0x04 DCT0 Page conflict 0x08 DCT1 Page hit 0x10 DCT1 Page miss 0x20 DCT1 Page Conflict - 0x40 Write request - 0x80 Read request name:mem_page_overflow type:bitmask default:0x03 0x01 DCT0 Page Table Overflow 0x02 DCT1 Page Table Overflow @@ -163,7 +166,7 @@ name:cacheblock type:bitmask default:0x3 0x04 Read Block (Dcache load miss refill) 0x08 Read Block Shared (Icache refill) 0x10 Read Block Modified (Dcache store miss refill) - 0x20 Change to Dirty (first store to clean block already in cache) + 0x20 Change-to-Dirty (first store to clean block already in cache) name:dataprefetch type:bitmask default:0x03 0x01 Cancelled prefetches 0x02 Prefetch attempts @@ -171,14 +174,16 @@ name:memreqtype type:bitmask default:0x8 0x01 Requests to non-cacheable (UC) memory 0x02 Requests to write-combining (WC) memory or WC buffer flushes to WB memory 0x80 Streaming store (SS) requests -name:systemreadresponse type:bitmask default:0x17 +name:systemreadresponse type:bitmask default:0x1f 0x01 Exclusive 0x02 Modified 0x04 Shared + 0x08 Owned 0x10 Data Error -name:l1_dtlb_miss_l2_hit type:bitmask default:0x03 +name:l1_dtlb_miss_l2_hit type:bitmask default:0x07 0x01 L2 4K TLB hit 0x02 L2 2M TLB hit + 0x04 L2 1G TLB hit (RevC) name:l1_l2_dtlb_miss type:bitmask default:0x07 0x01 4K TLB reload 0x02 2M TLB reload @@ -216,7 +221,7 @@ name:httransmit type:bitmask default:0xb 0x02 Data DWORD sent 0x04 Buffer release DWORD sent 0x08 Nop DW sent (idle) - 0x10 Address extension DWORD sent + 0x10 Address DWORD sent 0x20 Per packet CRC sent 0x80 SubLink Mask name:lock_ops type:bitmask default:0x0f @@ -289,7 +294,7 @@ name:cpu_read_lat_0_3 type:bitmask defau 0x01 Read block 0x02 Read block shared 0x04 Read block modified - 0x08 Change to Dirty + 0x08 Change-to-Dirty 0x10 From local node to node 0 0x20 From local node to node 1 0x40 From local node to node 2 @@ -298,7 +303,7 @@ name:cpu_read_lat_4_7 type:bitmask defau 0x01 Read block 0x02 Read block shared 0x04 Read block modified - 0x08 Change to Dirty + 0x08 Change-to-Dirty 0x10 From local node to node 4 0x20 From local node to node 5 0x40 From local node to node 6 @@ -334,9 +339,18 @@ name:l3_evict type:bitmask default:0x0f 0x02 Exclusive 0x04 Owned 0x08 Modified -name:icache_invalidated type:bitmask default:0x0f +name:icache_invalidated type:bitmask default:0x03 0x01 Invalidating probe that did not hit any in-flight instructions 0x02 Invalidating probe that hit one or more in-flight instructions - 0x04 SMC that did not hit any in-flight instructions - 0x08 SMC that hit one or more in-flight instructions +name:page_size_mismatches type:bitmask default:0x07 + 0x01 Guest page size is larger than the host page size + 0x02 MTRR mismatch + 0x04 Host page size is larger than the guest page size +name:retired_x87_fp type:bitmask default:0x07 + 0x01 Add/subtract ops + 0x02 Multiply ops + 0x04 Divide ops +name:ibs_op type:bitmask default:0x01 + 0x00 Using IBS OP cycle count mode + 0x01 Using IBS OP dispatch count mode |