[oprof-cvs] CVS: oprofile/events/mips/vr5432 events,1.1,1.2

[Philippe E. <ph...@us...>]

Update of /cvsroot/oprofile/oprofile/events/mips/vr5432
In directory sc8-pr-cvs3.sourceforge.net:/tmp/cvs-serv6366/events/mips/vr5432

Modified Files:
	events 
Log Message:
fix bug #1717298, many mips event number was in decimal but parsed as hexadecimal. Change the code so make check no longer accept decimal notation for field intended to be in hexadecimal. Comment out a bunch of events for mips/34K, they overlap and they does not make sense

Index: events
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/mips/vr5432/events,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -p -d -r1.1 -r1.2
--- events	12 Dec 2004 23:26:54 -0000	1.1
+++ events	19 Oct 2007 15:08:39 -0000	1.2
@@ -1,14 +1,14 @@
 #
 # VR5432 events
 #
-event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
-event:1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
-event:2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
-event:3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
-event:4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
-event:5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
-event:6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
-event:7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
-event:8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
-event:9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
-event:10 counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
+event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
+event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
+event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
+event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
+event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
+event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
+event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
+event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
+event:0xa counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted