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[oprof-cvs] CVS: oprofile/events/ppc64/970MP event_mappings, NONE, 1.1 events, NONE, 1.1 unit_masks, NONE, 1.1
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From: Maynard J. <may...@us...> - 2007-02-02 16:27:42
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Update of /cvsroot/oprofile/oprofile/events/ppc64/970MP In directory sc8-pr-cvs3.sourceforge.net:/tmp/cvs-serv10624/events/ppc64/970MP Added Files: event_mappings events unit_masks Log Message: Add specific support for PowerPC970MP --- NEW FILE: event_mappings --- # # Copyright OProfile authors # Copyright (c) International Business Machines, 2006. # Contributed by Dave Nomura <dc...@us...>. # #Mapping of event groups to MMCR values #Group Default event:0X001 mmcr0:0X0400C51E mmcr1:0X000000000A46F18C mmcra:0X00002001 #Group 1 pm_slice0, Time Slice 0 event:0X0010 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000 event:0X0011 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000 event:0X0012 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000 event:0X0013 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000 event:0X0014 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000 event:0X0015 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000 event:0X0016 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000 event:0X0017 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000 #Group 2 pm_eprof, Group for use with eprof event:0X0020 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0021 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0022 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0023 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0024 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0025 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0026 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0027 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000 #Group 3 pm_basic, Basic performance indicators event:0X0030 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0031 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0032 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0033 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0034 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0035 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0036 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000 event:0X0037 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000 #Group 4 pm_lsu, Information on the Load Store Unit event:0X0040 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000 event:0X0041 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000 event:0X0042 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000 event:0X0043 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000 event:0X0044 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000 event:0X0045 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000 event:0X0046 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000 event:0X0047 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000 #Group 5 pm_fpu1, Floating Point events event:0X0050 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000 event:0X0051 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000 event:0X0052 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000 event:0X0053 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000 event:0X0054 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000 event:0X0055 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000 event:0X0056 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000 event:0X0057 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000 #Group 6 pm_fpu2, Floating Point events event:0X0060 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000 event:0X0061 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000 event:0X0062 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000 event:0X0063 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000 event:0X0064 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000 event:0X0065 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000 event:0X0066 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000 event:0X0067 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000 #Group 7 pm_isu_rename, ISU Rename Pool Events event:0X0070 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000 event:0X0071 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000 event:0X0072 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000 event:0X0073 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000 event:0X0074 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000 event:0X0075 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000 event:0X0076 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000 event:0X0077 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000 #Group 8 pm_isu_queues1, ISU Rename Pool Events event:0X0080 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000 event:0X0081 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000 event:0X0082 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000 event:0X0083 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000 event:0X0084 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000 event:0X0085 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000 event:0X0086 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000 event:0X0087 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000 #Group 9 pm_isu_flow, ISU Instruction Flow Events event:0X0090 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000 event:0X0091 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000 event:0X0092 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000 event:0X0093 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000 event:0X0094 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000 event:0X0095 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000 event:0X0096 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000 event:0X0097 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000 #Group 10 pm_isu_work, ISU Indicators of Work Blockage event:0X00A0 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000 event:0X00A1 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000 event:0X00A2 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000 event:0X00A3 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000 event:0X00A4 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000 event:0X00A5 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000 event:0X00A6 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000 event:0X00A7 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000 #Group 11 pm_fpu3, Floating Point events by unit event:0X00B0 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000 event:0X00B1 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000 event:0X00B2 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000 event:0X00B3 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000 event:0X00B4 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000 event:0X00B5 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000 event:0X00B6 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000 event:0X00B7 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000 #Group 12 pm_fpu4, Floating Point events by unit event:0X00C0 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000 event:0X00C1 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000 event:0X00C2 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000 event:0X00C3 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000 event:0X00C4 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000 event:0X00C5 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000 event:0X00C6 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000 event:0X00C7 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000 #Group 13 pm_fpu5, Floating Point events by unit event:0X00D0 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000 event:0X00D1 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000 event:0X00D2 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000 event:0X00D3 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000 event:0X00D4 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000 event:0X00D5 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000 event:0X00D6 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000 event:0X00D7 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000 #Group 14 pm_fpu7, Floating Point events by unit event:0X00E0 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000 event:0X00E1 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000 event:0X00E2 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000 event:0X00E3 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000 event:0X00E4 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000 event:0X00E5 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000 event:0X00E6 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000 event:0X00E7 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000 #Group 15 pm_lsu_flush, LSU Flush Events event:0X00F0 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000 event:0X00F1 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000 event:0X00F2 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000 event:0X00F3 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000 event:0X00F4 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000 event:0X00F5 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000 event:0X00F6 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000 event:0X00F7 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000 #Group 16 pm_lsu_load1, LSU Load Events event:0X0100 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000 event:0X0101 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000 event:0X0102 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000 event:0X0103 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000 event:0X0104 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000 event:0X0105 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000 event:0X0106 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000 event:0X0107 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000 #Group 17 pm_lsu_store1, LSU Store Events event:0X0110 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000 event:0X0111 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000 event:0X0112 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000 event:0X0113 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000 event:0X0114 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000 event:0X0115 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000 event:0X0116 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000 event:0X0117 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000 #Group 18 pm_lsu_store2, LSU Store Events event:0X0120 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000 event:0X0121 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000 event:0X0122 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000 event:0X0123 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000 event:0X0124 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000 event:0X0125 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000 event:0X0126 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000 event:0X0127 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000 #Group 19 pm_lsu7, Information on the Load Store Unit event:0X0130 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000 event:0X0131 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000 event:0X0132 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000 event:0X0133 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000 event:0X0134 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000 event:0X0135 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000 event:0X0136 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000 event:0X0137 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000 #Group 20 pm_misc, Misc Events for testing event:0X0140 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000 event:0X0141 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000 event:0X0142 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000 event:0X0143 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000 event:0X0144 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000 event:0X0145 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000 event:0X0146 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000 event:0X0147 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000 #Group 21 pm_pe_bench1, PE Benchmarker group for FP analysis event:0X0150 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000 event:0X0151 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000 event:0X0152 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000 event:0X0153 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000 event:0X0154 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000 event:0X0155 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000 event:0X0156 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000 event:0X0157 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000 #Group 22 pm_pe_bench4, PE Benchmarker group for L1 and TLB event:0X0160 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0161 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0162 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0163 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0164 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0165 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0166 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0167 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000 #Group 23 pm_hpmcount1, Hpmcount group for L1 and TLB behavior event:0X0170 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0171 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0172 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0173 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0174 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0175 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0176 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000 event:0X0177 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000 #Group 24 pm_hpmcount2, Hpmcount group for computation event:0X0180 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000 event:0X0181 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000 event:0X0182 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000 event:0X0183 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000 event:0X0184 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000 event:0X0185 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000 event:0X0186 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000 event:0X0187 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000 #Group 25 pm_l1andbr, L1 misses and branch misspredict analysis event:0X0190 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000 event:0X0191 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000 event:0X0192 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000 event:0X0193 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000 event:0X0194 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000 event:0X0195 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000 event:0X0196 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000 event:0X0197 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000 #Group 26 pm_imix, Instruction mix: loads, stores and branches event:0X01A0 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000 event:0X01A1 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000 event:0X01A2 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000 event:0X01A3 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000 event:0X01A4 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000 event:0X01A5 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000 event:0X01A6 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000 event:0X01A7 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000 #Group 27 pm_branch, SLB and branch misspredict analysis event:0X01B0 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000 event:0X01B1 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000 event:0X01B2 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000 event:0X01B3 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000 event:0X01B4 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000 event:0X01B5 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000 event:0X01B6 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000 event:0X01B7 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000 #Group 28 pm_data, data source and LMQ event:0X01C0 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000 event:0X01C1 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000 event:0X01C2 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000 event:0X01C3 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000 event:0X01C4 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000 event:0X01C5 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000 event:0X01C6 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000 event:0X01C7 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000 #Group 29 pm_tlb, TLB and LRQ plus data prefetch event:0X01D0 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000 event:0X01D1 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000 event:0X01D2 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000 event:0X01D3 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000 event:0X01D4 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000 event:0X01D5 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000 event:0X01D6 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000 event:0X01D7 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000 #Group 30 pm_isource, inst source and tablewalk event:0X01E0 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000 event:0X01E1 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000 event:0X01E2 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000 event:0X01E3 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000 event:0X01E4 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000 event:0X01E5 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000 event:0X01E6 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000 event:0X01E7 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000 #Group 31 pm_sync, Sync and SRQ event:0X01F0 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000 event:0X01F1 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000 event:0X01F2 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000 event:0X01F3 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000 event:0X01F4 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000 event:0X01F5 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000 event:0X01F6 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000 event:0X01F7 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000 #Group 32 pm_ierat, IERAT event:0X0200 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000 event:0X0201 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000 event:0X0202 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000 event:0X0203 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000 event:0X0204 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000 event:0X0205 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000 event:0X0206 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000 event:0X0207 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000 #Group 33 pm_derat, DERAT event:0X0210 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000 event:0X0211 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000 event:0X0212 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000 event:0X0213 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000 event:0X0214 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000 event:0X0215 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000 event:0X0216 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000 event:0X0217 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000 #Group 34 pm_mark1, Information on marked instructions event:0X0220 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001 event:0X0221 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001 event:0X0222 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001 event:0X0223 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001 event:0X0224 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001 event:0X0225 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001 event:0X0226 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001 event:0X0227 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001 #Group 35 pm_mark2, Marked Instructions Processing Flow event:0X0230 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001 event:0X0231 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001 event:0X0232 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001 event:0X0233 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001 event:0X0234 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001 event:0X0235 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001 event:0X0236 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001 event:0X0237 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001 #Group 36 pm_mark3, Marked Stores Processing Flow event:0X0240 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001 event:0X0241 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001 event:0X0242 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001 event:0X0243 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001 event:0X0244 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001 event:0X0245 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001 event:0X0246 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001 event:0X0247 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001 #Group 37 pm_lsu_mark1, Load Store Unit Marked Events event:0X0250 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001 event:0X0251 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001 event:0X0252 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001 event:0X0253 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001 event:0X0254 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001 event:0X0255 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001 event:0X0256 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001 event:0X0257 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001 #Group 38 pm_lsu_mark2, Load Store Unit Marked Events event:0X0260 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001 event:0X0261 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001 event:0X0262 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001 event:0X0263 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001 event:0X0264 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001 event:0X0265 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001 event:0X0266 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001 event:0X0267 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001 #Group 39 pm_fxu1, Fixed Point events by unit event:0X0270 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000 event:0X0271 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000 event:0X0272 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000 event:0X0273 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000 event:0X0274 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000 event:0X0275 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000 event:0X0276 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000 event:0X0277 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000 #Group 40 pm_fxu2, Fixed Point events by unit event:0X0280 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000 event:0X0281 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000 event:0X0282 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000 event:0X0283 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000 event:0X0284 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000 event:0X0285 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000 event:0X0286 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000 event:0X0287 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000 #Group 41 pm_ifu, pm_ifu event:0X0290 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000 event:0X0291 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000 event:0X0292 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000 event:0X0293 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000 event:0X0294 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000 event:0X0295 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000 event:0X0296 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000 event:0X0297 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000 #Group 42 pm_cpi_stack1, CPI stack analysis event:0X02A0 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000 event:0X02A1 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000 event:0X02A2 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000 event:0X02A3 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000 event:0X02A4 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000 event:0X02A5 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000 event:0X02A6 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000 event:0X02A7 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000 #Group 43 pm_cpi_stack2, CPI stack analysis event:0X02B0 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000 event:0X02B1 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000 event:0X02B2 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000 event:0X02B3 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000 event:0X02B4 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000 event:0X02B5 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000 event:0X02B6 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000 event:0X02B7 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000 #Group 44 pm_cpi_stack3, CPI stack analysis event:0X02C0 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000 event:0X02C1 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000 event:0X02C2 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000 event:0X02C3 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000 event:0X02C4 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000 event:0X02C5 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000 event:0X02C6 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000 event:0X02C7 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000 #Group 45 pm_cpi_stack4, CPI stack analysis event:0X02D0 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000 event:0X02D1 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000 event:0X02D2 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000 event:0X02D3 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000 event:0X02D4 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000 event:0X02D5 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000 event:0X02D6 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000 event:0X02D7 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000 #Group 46 pm_cpi_stack5, CPI stack analysis event:0X02E0 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000 event:0X02E1 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000 event:0X02E2 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000 event:0X02E3 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000 event:0X02E4 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000 event:0X02E5 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000 event:0X02E6 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000 event:0X02E7 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000 #Group 47 pm_data2, data source and LMQ event:0X02F0 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000 event:0X02F1 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000 event:0X02F2 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000 event:0X02F3 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000 event:0X02F4 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000 event:0X02F5 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000 event:0X02F6 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000 event:0X02F7 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000 #Group 48 pm_fetch_branch, Instruction fetch and branch events event:0X0300 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000 event:0X0301 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000 event:0X0302 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000 event:0X0303 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000 event:0X0304 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000 event:0X0305 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000 event:0X0306 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000 event:0X0307 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000 #Group 49 pm_l1l2_miss, L1 and L2 miss events event:0X0310 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000 event:0X0311 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000 event:0X0312 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000 event:0X0313 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000 event:0X0314 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000 event:0X0315 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000 event:0X0316 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000 event:0X0317 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000 #Group 50 pm_mp_data, data source and LMQ for 970mp event:0X0320 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000 event:0X0321 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000 event:0X0322 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000 event:0X0323 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000 event:0X0324 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000 event:0X0325 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000 event:0X0326 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000 event:0X0327 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000 #Group 51 pm_mp_data2, data source and LMQ for 970mp event:0X0330 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000 event:0X0331 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000 event:0X0332 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000 event:0X0333 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000 event:0X0334 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000 event:0X0335 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000 event:0X0336 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000 event:0X0337 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000 #Group 52 pm_mp_data_from, Data From L2 instruction for 970mp event:0X0340 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000 event:0X0341 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000 event:0X0342 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000 event:0X0343 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000 event:0X0344 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000 event:0X0345 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000 event:0X0346 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000 event:0X0347 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000 #Group 53 pm_mp_mark_data_from, Marked Data From L2 instruction for 970mp event:0X0350 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001 event:0X0351 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001 event:0X0352 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001 event:0X0353 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001 event:0X0354 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001 event:0X0355 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001 event:0X0356 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001 event:0X0357 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001 --- NEW FILE: events --- #PPC64 PowerPC970 events # # Copyright OProfile authors # Copyright (c) International Business Machines, 2006. # Contributed by Dave Nomura <dc...@us...>. # # # Within each group the event names must be unique. Each event in a group is # assigned to a unique counter. The groups are from the groups defined in the # Performance Monitor Unit user guide for this processor. # # Only events within the same group can be selected simultaneously. # Each event is given a unique event number. The event number is used by the # OProfile code to resolve event names for the post-processing. This is done # to preserve compatibility with the rest of the OProfile code. The event # numbers are formatted as follows: <group_num>concat(<counter for the event>). #Group Default event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles #Group 1 pm_slice0, Time Slice 0 event:0X0010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles event:0X0011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles event:0X0012 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP1 : (Group 1 pm_slice0) Completion stopped event:0X0013 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_slice0) Instructions completed event:0X0014 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP1 : (Group 1 pm_slice0) One or more PPC instruction completed event:0X0015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles event:0X0016 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP1 : (Group 1 pm_slice0) Group completed event:0X0017 counters:7 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP1 : (Group 1 pm_slice0) Group dispatch rejected #Group 2 pm_eprof, Group for use with eprof event:0X0020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles event:0X0021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles event:0X0022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses event:0X0023 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP2 : (Group 2 pm_eprof) L1 D cache entries invalidated from L2 event:0X0024 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP2 : (Group 2 pm_eprof) Instructions dispatched event:0X0025 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP2 : (Group 2 pm_eprof) Instructions completed event:0X0026 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache store references event:0X0027 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load references #Group 3 pm_basic, Basic performance indicators event:0X0030 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed event:0X0031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles event:0X0032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses event:0X0033 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP3 : (Group 3 pm_basic) L1 D cache entries invalidated from L2 event:0X0034 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_basic) Instructions dispatched event:0X0035 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed event:0X0036 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache store references event:0X0037 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache load references #Group 4 pm_lsu, Information on the Load Store Unit event:0X0040 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP4 : (Group 4 pm_lsu) LRQ unaligned load flushes event:0X0041 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP4 : (Group 4 pm_lsu) SRQ unaligned store flushes event:0X0042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles event:0X0043 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP4 : (Group 4 pm_lsu) Instructions completed event:0X0044 counters:4 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP4 : (Group 4 pm_lsu) SRQ flushes event:0X0045 counters:5 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP4 : (Group 4 pm_lsu) LRQ flushes event:0X0046 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP4 : (Group 4 pm_lsu) L1 D cache store references event:0X0047 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP4 : (Group 4 pm_lsu) L1 D cache load references #Group 5 pm_fpu1, Floating Point events event:0X0050 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP5 : (Group 5 pm_fpu1) FPU executed FDIV instruction event:0X0051 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP5 : (Group 5 pm_fpu1) FPU executed multiply-add instruction event:0X0052 counters:2 um:zero minimum:1000 name:PM_FPU_FEST_GRP5 : (Group 5 pm_fpu1) FPU executed FEST instruction event:0X0053 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP5 : (Group 5 pm_fpu1) FPU produced a result event:0X0054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles event:0X0055 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP5 : (Group 5 pm_fpu1) FPU executed FSQRT instruction event:0X0056 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP5 : (Group 5 pm_fpu1) Instructions completed event:0X0057 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP5 : (Group 5 pm_fpu1) FPU executing FMOV or FEST instructions #Group 6 pm_fpu2, Floating Point events event:0X0060 counters:0 um:zero minimum:1000 name:PM_FPU_DENORM_GRP6 : (Group 6 pm_fpu2) FPU received denormalized data event:0X0061 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP6 : (Group 6 pm_fpu2) FPU stalled in pipe3 event:0X0062 counters:2 um:zero minimum:10000 name:PM_CYC_GRP6 : (Group 6 pm_fpu2) Processor cycles event:0X0063 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP6 : (Group 6 pm_fpu2) Instructions completed event:0X0064 counters:4 um:zero minimum:1000 name:PM_FPU_ALL_GRP6 : (Group 6 pm_fpu2) FPU executed add, mult, sub, cmp or sel instruction event:0X0065 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP6 : (Group 6 pm_fpu2) FPU executed store instruction event:0X0066 counters:6 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP6 : (Group 6 pm_fpu2) FPU executed FRSP or FCONV instructions event:0X0067 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP6 : (Group 6 pm_fpu2) LSU executed Floating Point load instruction #Group 7 pm_isu_rename, ISU Rename Pool Events event:0X0070 counters:0 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles XER mapper full event:0X0071 counters:1 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles CR logical operation mapper full event:0X0072 counters:2 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles CR issue queue full event:0X0073 counters:3 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles group dispatch blocked by scoreboard event:0X0074 counters:4 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles LR/CTR mapper full event:0X0075 counters:5 um:zero minimum:1000 name:PM_INST_DISP_GRP7 : (Group 7 pm_isu_rename) Instructions dispatched event:0X0076 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP7 : (Group 7 pm_isu_rename) Instructions completed event:0X0077 counters:7 um:zero minimum:10000 name:PM_CYC_GRP7 : (Group 7 pm_isu_rename) Processor cycles #Group 8 pm_isu_queues1, ISU Rename Pool Events event:0X0080 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FPU0 issue queue full event:0X0081 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FPU1 issue queue full event:0X0082 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FXU0/LS0 queue full event:0X0083 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FXU1/LS1 queue full event:0X0084 counters:4 um:zero minimum:10000 name:PM_CYC_GRP8 : (Group 8 pm_isu_queues1) Processor cycles event:0X0085 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP8 : (Group 8 pm_isu_queues1) Instructions completed event:0X0086 counters:6 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles LRQ full event:0X0087 counters:7 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles SRQ full #Group 9 pm_isu_flow, ISU Instruction Flow Events event:0X0090 counters:0 um:zero minimum:1000 name:PM_INST_DISP_GRP9 : (Group 9 pm_isu_flow) Instructions dispatched event:0X0091 counters:1 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_isu_flow) Processor cycles event:0X0092 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP9 : (Group 9 pm_isu_flow) FXU0 produced a result event:0X0093 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP9 : (Group 9 pm_isu_flow) FXU1 produced a result event:0X0094 counters:4 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP9 : (Group 9 pm_isu_flow) Group dispatch valid event:0X0095 counters:5 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP9 : (Group 9 pm_isu_flow) Group dispatch rejected event:0X0096 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP9 : (Group 9 pm_isu_flow) Instructions completed event:0X0097 counters:7 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_isu_flow) Processor cycles #Group 10 pm_isu_work, ISU Indicators of Work Blockage event:0X00A0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP10 : (Group 10 pm_isu_work) Cycles GCT empty event:0X00A1 counters:1 um:zero minimum:1000 name:PM_WORK_HELD_GRP10 : (Group 10 pm_isu_work) Work held event:0X00A2 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP10 : (Group 10 pm_isu_work) Completion stopped event:0X00A3 counters:3 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off and external interrupt pending event:0X00A4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP10 : (Group 10 pm_isu_work) Processor cycles event:0X00A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP10 : (Group 10 pm_isu_work) Instructions completed event:0X00A6 counters:6 um:zero minimum:1000 name:PM_EE_OFF_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off event:0X00A7 counters:7 um:zero minimum:1000 name:PM_EXT_INT_GRP10 : (Group 10 pm_isu_work) External interrupts #Group 11 pm_fpu3, Floating Point events by unit event:0X00B0 counters:0 um:zero minimum:1000 name:PM_FPU0_FDIV_GRP11 : (Group 11 pm_fpu3) FPU0 executed FDIV instruction event:0X00B1 counters:1 um:zero minimum:1000 name:PM_FPU1_FDIV_GRP11 : (Group 11 pm_fpu3) FPU1 executed FDIV instruction event:0X00B2 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP11 : (Group 11 pm_fpu3) FPU0 executed FRSP or FCONV instructions event:0X00B3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP11 : (Group 11 pm_fpu3) FPU1 executed FRSP or FCONV instructions event:0X00B4 counters:4 um:zero minimum:1000 name:PM_FPU0_FMA_GRP11 : (Group 11 pm_fpu3) FPU0 executed multiply-add instruction event:0X00B5 counters:5 um:zero minimum:1000 name:PM_FPU1_FMA_GRP11 : (Group 11 pm_fpu3) FPU1 executed multiply-add instruction event:0X00B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP11 : (Group 11 pm_fpu3) Instructions completed event:0X00B7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP11 : (Group 11 pm_fpu3) Processor cycles #Group 12 pm_fpu4, Floating Point events by unit event:0X00C0 counters:0 um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU0 executed FSQRT instruction event:0X00C1 counters:1 um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU1 executed FSQRT instruction event:0X00C2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP12 : (Group 12 pm_fpu4) FPU0 produced a result event:0X00C3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP12 : (Group 12 pm_fpu4) FPU1 produced a result event:0X00C4 counters:4 um:zero minimum:1000 name:PM_FPU0_ALL_GRP12 : (Group 12 pm_fpu4) FPU0 executed add, mult, sub, cmp or sel instruction event:0X00C5 counters:5 um:zero minimum:1000 name:PM_FPU1_ALL_GRP12 : (Group 12 pm_fpu4) FPU1 executed add, mult, sub, cmp or sel instruction event:0X00C6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP12 : (Group 12 pm_fpu4) Instructions completed event:0X00C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP12 : (Group 12 pm_fpu4) Processor cycles #Group 13 pm_fpu5, Floating Point events by unit event:0X00D0 counters:0 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP13 : (Group 13 pm_fpu5) FPU0 received denormalized data event:0X00D1 counters:1 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP13 : (Group 13 pm_fpu5) FPU1 received denormalized data event:0X00D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FMOV_FEST_GRP13 : (Group 13 pm_fpu5) FPU0 executed FMOV or FEST instructions event:0X00D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FMOV_FEST_GRP13 : (Group 13 pm_fpu5) FPU1 executing FMOV or FEST instructions event:0X00D4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP13 : (Group 13 pm_fpu5) Processor cycles event:0X00D5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP13 : (Group 13 pm_fpu5) Instructions completed event:0X00D6 counters:6 um:zero minimum:1000 name:PM_FPU0_FEST_GRP13 : (Group 13 pm_fpu5) FPU0 executed FEST instruction event:0X00D7 counters:7 um:zero minimum:1000 name:PM_FPU1_FEST_GRP13 : (Group 13 pm_fpu5) FPU1 executed FEST instruction #Group 14 pm_fpu7, Floating Point events by unit event:0X00E0 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP14 : (Group 14 pm_fpu7) FPU0 stalled in pipe3 event:0X00E1 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP14 : (Group 14 pm_fpu7) FPU1 stalled in pipe3 event:0X00E2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP14 : (Group 14 pm_fpu7) FPU0 produced a result event:0X00E3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP14 : (Group 14 pm_fpu7) FPU1 produced a result event:0X00E4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_fpu7) Processor cycles event:0X00E5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP14 : (Group 14 pm_fpu7) Instructions completed event:0X00E6 counters:6 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_fpu7) Processor cycles event:0X00E7 counters:7 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP14 : (Group 14 pm_fpu7) FPU0 executed FPSCR instruction #Group 15 pm_lsu_flush, LSU Flush Events event:0X00F0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP15 : (Group 15 pm_lsu_flush) LSU0 LRQ flushes event:0X00F1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP15 : (Group 15 pm_lsu_flush) LSU1 LRQ flushes event:0X00F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles event:0X00F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles event:0X00F4 counters:4 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_flush) LSU0 SRQ flushes event:0X00F5 counters:5 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_flush) LSU1 SRQ flushes event:0X00F6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP15 : (Group 15 pm_lsu_flush) Instructions completed event:0X00F7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles #Group 16 pm_lsu_load1, LSU Load Events event:0X0100 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP16 : (Group 16 pm_lsu_load1) LSU0 unaligned load flushes event:0X0101 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP16 : (Group 16 pm_lsu_load1) LSU1 unaligned load flushes event:0X0102 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load references event:0X0103 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load references event:0X0104 counters:4 um:zero minimum:10000 name:PM_CYC_GRP16 : (Group 16 pm_lsu_load1) Processor cycles event:0X0105 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP16 : (Group 16 pm_lsu_load1) Instructions completed event:0X0106 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load misses event:0X0107 counters:7 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load misses #Group 17 pm_lsu_store1, LSU Store Events event:0X0110 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP17 : (Group 17 pm_lsu_store1) LSU0 unaligned store flushes event:0X0111 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP17 : (Group 17 pm_lsu_store1) LSU1 unaligned store flushes event:0X0112 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP17 : (Group 17 pm_lsu_store1) LSU0 L1 D cache store references event:0X0113 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP17 : (Group 17 pm_lsu_store1) LSU1 L1 D cache store references event:0X0114 counters:4 um:zero minimum:10000 name:PM_CYC_GRP17 : (Group 17 pm_lsu_store1) Processor cycles event:0X0115 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP17 : (Group 17 pm_lsu_store1) Instructions completed event:0X0116 counters:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP17 : (Group 17 pm_lsu_store1) L1 D cache store misses event:0X0117 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP17 : (Group 17 pm_lsu_store1) L1 D cache entries invalidated from L2 #Group 18 pm_lsu_store2, LSU Store Events event:0X0120 counters:0 um:zero minimum:1000 name:PM_LSU0_SRQ_STFWD_GRP18 : (Group 18 pm_lsu_store2) LSU0 SRQ store forwarded event:0X0121 counters:1 um:zero minimum:1000 name:PM_LSU1_SRQ_STFWD_GRP18 : (Group 18 pm_lsu_store2) LSU1 SRQ store forwarded event:0X0122 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP18 : (Group 18 pm_lsu_store2) LSU0 L1 D cache store references event:0X0123 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP18 : (Group 18 pm_lsu_store2) LSU1 L1 D cache store references event:0X0124 counters:4 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP18 : (Group 18 pm_lsu_store2) LSU0 busy event:0X0125 counters:5 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_lsu_store2) Processor cycles event:0X0126 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP18 : (Group 18 pm_lsu_store2) Instructions completed event:0X0127 counters:7 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_lsu_store2) Processor cycles #Group 19 pm_lsu7, Information on the Load Store Unit event:0X0130 counters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU0 DERAT misses event:0X0131 counters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU1 DERAT misses event:0X0132 counters:2 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles event:0X0133 counters:3 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles event:0X0134 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP19 : (Group 19 pm_lsu7) Instructions completed event:0X0135 counters:5 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles event:0X0136 counters:6 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP19 : (Group 19 pm_lsu7) L1 reload data source valid event:0X0137 counters:7 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles #Group 20 pm_misc, Misc Events for testing event:0X0140 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP20 : (Group 20 pm_misc) Cycles GCT empty event:0X0141 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP20 : (Group 20 pm_misc) Cycles LMQ and SRQ empty event:0X0142 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP20 : (Group 20 pm_misc) Hypervisor Cycles event:0X0143 counters:3 um:zero minimum:10000 name:PM_CYC_GRP20 : (Group 20 pm_misc) Processor cycles event:0X0144 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP20 : (Group 20 pm_misc) One or more PPC instruction completed event:0X0145 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP20 : (Group 20 pm_misc) Instructions completed event:0X0146 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP20 : (Group 20 pm_misc) Group completed event:0X0147 counters:7 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP20 : (Group 20 pm_misc) Time Base bit transition #Group 21 pm_pe_bench1, PE Benchmarker group for FP analysis event:0X0150 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP21 : (Group 21 pm_pe_bench1) FPU executed FDIV instruction event:0X0151 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP21 : (Group 21 pm_pe_bench1) FPU executed multiply-add instruction event:0X0152 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP21 : (Group 21 pm_pe_bench1) FXU produced a result event:0X0153 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP21 : (Group 21 pm_pe_bench1) FPU produced a result event:0X0154 counters:4 um:zero minimum:10000 name:PM_CYC_GRP21 : (Group 21 pm_pe_bench1) Processor cycles event:0X0155 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP21 : (Group 21 pm_pe_bench1) FPU executed FSQRT instruction event:0X0156 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP21 : (Group 21 pm_pe_bench1) Instructions completed event:0X0157 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP21 : (Group 21 pm_pe_bench1) FPU executing FMOV or FEST instructions #Group 22 pm_pe_bench4, PE Benchmarker group for L1 and TLB event:0X0160 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Data TLB misses event:0X0161 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Instruction TLB misses event:0X0162 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load misses event:0X0163 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache store misses event:0X0164 counters:4 um:zero minimum:10000 name:PM_CYC_GRP22 : (Group 22 pm_pe_bench4) Processor cycles event:0X0165 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP22 : (Group 22 pm_pe_bench4) Instructions completed event:0X0166 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache store references event:0X0167 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load references #Group 23 pm_hpmcount1, Hpmcount group for L1 and TLB behavior event:0X0170 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP23 : (Group 23 pm_hpmcount1) Data TLB misses event:0X0171 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP23 : (Group 23 pm_hpmcount1) Cycles LMQ and SRQ empty event:0X0172 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache load misses event:0X0173 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache store misses event:0X0174 counters:4 um:zero minimum:10000 name:PM_CYC_GRP23 : (Group 23 pm_hpmcount1) Processor cycles event:0X0175 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP23 : (Group 23 pm_hpmcount1) Instructions completed event:0X0176 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache store references event:0X0177 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache load references #Group 24 pm_hpmcount2, Hpmcount group for computation event:0X0180 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP24 : (Group 24 pm_hpmcount2) FPU executed FDIV instruction event:0X0181 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP24 : (Group 24 pm_hpmcount2) FPU executed multiply-add instruction event:0X0182 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP24 : (Group 24 pm_hpmcount2) FPU0 produced a result event:0X0183 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP24 : (Group 24 pm_hpmcount2) FPU1 produced a result event:0X0184 counters:4 um:zero minimum:10000 name:PM_CYC_GRP24 : (Group 24 pm_hpmcount2) Processor cycles event:0X0185 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP24 : (Group 24 pm_hpmcount2) FPU executed store instruction event:0X0186 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP24 : (Group 24 pm_hpmcount2) Instructions completed event:0X0187 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP24 : (Group 24 pm_hpmcount2) LSU executed Floating Point load instruction #Group 25 pm_l1andbr, L1 misses and branch misspredict analysis event:0X0190 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP25 : (Group 25 pm_l1andbr) Instructions completed event:0X0191 counters:1 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_l1andbr) Processor cycles event:0X0192 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP25 : (Group 25 pm_l1andbr) L1 D cache load misses event:0X0193 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP25 : (Group 25 pm_l1andbr) Branches issued event:0X0194 counters:4 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP25 : (Group 25 pm_l1andbr) LSU0 busy event:0X0195 counters:5 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_l1andbr) Processor cycles event:0X0196 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP25 : (Group 25 pm_l1andbr) Branch mispredictions due to CR bit setting event:0X0197 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP25 : (Group 25 pm_l1andbr) Branch mispredictions due to target address #Group 26 pm_imix, Instruction mix: loads, stores and branches event:0X01A0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP26 : (Group 26 pm_imix) Instructions completed event:0X01A1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_imix) Processor cycles event:0X01A2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP26 : (Group 26 pm_imix) L1 D cache load misses event:0X01A3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP26 : (Group 26 pm_imix) Branches issued event:0X01A4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_imix) Processor cycles event:0X01A5 counters:5 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP26 : (Group 26 pm_imix) LSU0 busy event:0X01A6 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP26 : (Group 26 pm_imix) L1 D cache store references event:0X01A7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP26 : (Group 26 pm_imix) L1 D cache load references #Group 27 pm_branch, SLB and branch misspredict analysis event:0X01B0 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP27 : (Group 27 pm_branch) Run cycles event:0X01B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP27 : (Group 27 pm_branch) Data SLB misses event:0X01B2 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP27 : (Group 27 pm_branch) Branches issued event:0X01... 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