From: William C. <wc...@nc...> - 2004-10-05 20:35:13
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Carl Love wrote: > Will: > > Unlike Intel where there is a separate register to program the event for > each performance counter, the Power 4 and Power 5 have two registers > that hold the events for all counters. These registers are called mmcr0 > and mmcr1. Additionally, there are bits in these registers that > configure the Muxes that control the routing of the event bits to the > performance counters. Due to routing conflicts, you can not arbitrarily > route any performance event to any register. Hence, you end up selecting > a set of events you want to program. There is a program that is used to > try and figure out the mux settings and mapping of the events to the > counters. A program is used because the mapping is complex. If it is > possible to do the map/route the signals for the selected events, you > get back the mmcr register values other wise it fails. The group of > events are then referred to as a group and are defined by the mmcr > register values. Hence you cannot select events from different groups > because the register settings are different for each group and there is > one set of registers to hold the events. Furthermore, the groups that > were used are the set of groups that the hardware team has put together > and verified a working. I chose not to include the program that would > try to create the mmcr register settings from an arbitrary set of events > because I can't guarantee that the mapping will succeed. > > I am looking for some publicly available Power 5 architecture links that > I can send you. I have some on Power 4 that I will send to you. > > Carl Love Okay so this is something like the Pentium II where there is a single register holding the event information. However, there are restrictions on events muxs selection. The manual I am looking at (archpub3.pdf) doesn't go into much detail. It says "see Book IV" and I haven't found a copy of book IV on the web. It shows 4 bits for each of the eight counters. -Will |