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Re: [openMSX-devel] [bug 689038] Parallax logo in Blade Lords / HR bit
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From: Jon De S. <jo...@ms...> - 2003-04-24 21:33:47
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Hello Wouter,
The VDP doesn't have a pin to create a /WAIT state of the CPU during IO. However
it might be possible that the MSXengine creates a waitstate during IO to the VDP
ports.
Anyway, I've measured with the oscilloscope to be sure: "IN A,(#99)" takes
indeed only 12 CPUclks.
About the HR bit: when looking at the VDP databook, they talk about
"Display time" : 1024 clks (nonText) or 960 clks (Text)
"Right border" : 59 clks (nonText) or 87 clks (Text)
"Right erase" : 27 clks
"HSync" : 100 clks
"Left erase" : 102 clks
"Left border" : 56 clks (nonText) or 92 clks (Text)
---- ---
Total: 1368 1368
Probably the HR bit is not set during the complete 1368-1024=344 clks, but only
during a part of it corresponding to one of the smaller horizontal zones.
CU tomorrow,
Jon
Wouter Vermaelen wrote:
> ...
> in a,(#99) 12 T-States
> and e 5
> jr z,loop 8 (don't jump)
> outi 18
> jp nz,loop 11
> in a,(#99) 12
> and e 5
> jr z,loop 8 (don't jump)
> outi 18
>
> The time between the two "in a,(#99)" instructions is 54 CPU clock cycles.
> This corresponds to 324 VDP clock cycles. The HR bit remains high for 344
> (1368 - 1024) cycles. So this behaviour is possible.
>
> However on a real MSX this routine has no timing problems. So either
> - CPU timimg is wrong:
> I verified the timing of the instructions and they should be ok.
> I'm not 100% sure about the I/O instructions to the VDP, maybe
> there is some extra delay inserted somewhere.
> - HR bit stays high a little too long
> The difference is only 20 VDP clock cycles (3.3 CPU cycles), so we have to
> be really accurate to get this right.
>
> Wouter
>
> BTW: On R800 this goes completely wrong because the extra delay while
> accessing the VDP is not implemented.
>
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