From: Maarten t. H. <ma...@tr...> - 2002-12-31 15:56:25
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On Tuesday 31 December 2002 11:21, Wouter Vermaelen wrote: > > The alternative is to make sure all calls occur in timestamp order. T= his > > means the Z80 is not allowed to perform I/O past the next sync point, > > even if the instruction that performs the I/O starts before the next = sync > > point. Any ideas how this can be implemented? It would really help me= in > > trying to get the VDP code as clear as possible. > > Unfortunately this is not so easy to solve. The CPU emulation must be a= ble > to stop and resume in the middle of an instruction. I have a few ideas = to > implement this. Even without a noticeable performance hit I hope. Howev= er > it requires a major rewrite of the current CPU code and thus also a lot= of > time. Resuming in the middle of an instruction is one option. It is also possib= le to=20 abort the instruction and when the Z80 is scheduled again, restart it ins= tead=20 of resuming it. That might simpify the state kept in the Z80 class. Aborting an instruction means that before you do I/O (both I/O mapped and= =20 memory mapped, both read and write) you check the I/O timestamp is lower = than=20 the end timestamp of the Z80 scheduled time. If this is not the case, any= =20 processing done for this instruction is discarded and control is returned= to=20 the scheduler. Since most (all?) instructions only change the Z80 state a= fter=20 I/O, I hope this won't be too hard. > How urgent do you need this? I could implement some temporally hacks > if you like (for example perform IO at the same time as the start of th= e > instruction). The workaround from your other mail is good enough for me to continue=20 debugging the VDP code. However, we want near-perfect emulation, so the i= ssue=20 should be solved one day. Since it is not a simple issue, I don't mind if= it=20 takes some time. Bye, =09=09Maarten |