[Openbts-discuss] HELP: Sending 2 channels to USRP1 (OpenBTS application)

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Hello,

I'm trying to get 2 channels working (for TX right now) on USRP1 with 2 RFX
boards.

Starting from the transceiver and going to the radio front-end, my TX data
path is as follow for channel 0:
- channel 0 tx data is received from Openbts core on data socket 5702, then
put into mTransmitQueue
- the tx burst is "radioified" into a sendbuffer
- when there is enough tx burst data in sendbuffer (625 samples), the tx
burst data is packetized into an USB packet -per the usb inband signaling
doc- with parameter CHAN=0 in writeSamples
- the USB packet is sent to the USRP

Similarly for channel 1:
- channel 1 tx data is received from Openbts core on data socket 5704, then
put into mTransmitQueueCh1
- the tx burst is "radioified" into a sendbufferCh1
- when there is enough tx burst data in sendbufferCh1 (625 samples), the tx
burst data is packetized into an USB packet -per the usb inband signaling
doc- with parameter CHAN=1 in writeSamples
- the USB packet is sent to the USRP

For ease of debug, I currently have set channel 1 data on the OpenBTS core
side to be the same as channel 0.

In the USRP, i have done the following:
In USRPDevice.cpp, modified 'make' in order to support 2 channels
    m_uRx = usrp_standard_rx_sptr(usrp_standard_rx::make(0,decimRate,*
2,rx_mux*,

usrp_standard_rx::FPGA_MODE_NORMAL,
                                                         1024,16*8,rbf));
    m_uTx = usrp_standard_tx_sptr(usrp_standard_tx::make(0,decimRate*2,*2*,*
tx_mux*,
                                                         1024,16*8,rbf));

I also modified start() to set-up the daughterboard properly, incl the
muxing of DDC/DUC to ADC/DAC. see code below.

At this time, I manage only to get channel 0 to work:
- with tx_mux = 0xba98: I can see channel 0 on TX A. But can not see
anything on TX B, while expected to see channel 1.
- with tx_mux=0x98ba: I can see channel 0 on TX B. But can not see anything
on TX A, while expected to see channel 1.
- with tx_mux=0x9898: I can see channel 0 on both TX A and TX B
-with tx_mux=0xbaba: I do not see channel 0, which is expected. But I can't
see channel 1 either on either TX board.

So it looks like I currently can't get the channel 1 properly to the USRP.
I have followed the USB inband signaling doc:

  Chan  5-bit logical channel number.  Channel number 0x1f is reserved
        for control information.  See "Control Channel" below.  Other
        channels are "data channels."  Each data channel is logically
        independent of the others.  A data channel payload field
        contains a sequence of homogeneous samples.  The format of the
        samples is determined by the configuration associated with the
        given channel.  It is often the case that the payload field
        contains 32-bit complex samples, each containing 16-bit real
        and imaginary components.

Can someone help explain what I did wrong?
How a second channel data shall be sent from the PC to the USRP?

Thank you for your help
Rgds
N.

Here is the mods I did in USRPDevice.cpp start()

// *SIDE B** *SIDE A**
// DAC3 DAC2 DAC1 DAC0
// 1001 1000 1011 1010
// N=1  N=0  N=3  N=2
// Q0   I0   Q1   I1
// Channel0  Channel1
// on SideB  on SideA
// E|NNN
// 0x98ba

// *SIDE B** *SIDE A**
// DAC3 DAC2 DAC1 DAC0
// 1011 1010 1001 1000
// N=3  N=2  N=1  N=0
// Q1   I1   Q0   I0
// Channel1  Channel0
// on SideB  on SideA
// E|NNN
// 0xba98

const int USRPDevice::tx_mux=0xbaba;

//  Channel1  Channel0
//  Q1   I1   Q0   I0
//   1    0    3    2
// ADC1 ADC0 ADC3 ADC2
// *SIDE A** *SIDE B**
// 0x1032

const int USRPDevice::rx_mux=0x1032;

  // TX on daughter A
  writeLock.lock();
  // power up and configure daughterboards
  m_uTx->_write_oe(0,0,0xffff);
  m_uTx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
  //m_uTx->write_io(0,ENABLE,(POWER_UP|RX_TXN|ENABLE)); /* POWER_UP
inverted */
  m_uTx->write_io(0, ENABLE, ENABLE | RX_TXN | POWER_UP); /* power up
inverted */
  m_uTx->_write_fpga_reg(FR_ATR_MASK_0 ,0);//RX_TXN|ENABLE);
  m_uTx->_write_fpga_reg(FR_ATR_TXVAL_0,0);//,0 |ENABLE);
  m_uTx->_write_fpga_reg(FR_ATR_RXVAL_0,0);//,RX_TXN|0);
  m_uTx->_write_fpga_reg(40,0);
  m_uTx->_write_fpga_reg(42,0);
  m_uTx->set_pga(0,m_uTx->pga_min()); // should be 20dB
  m_uTx->set_pga(1,m_uTx->pga_min());
  m_uTx->set_mux(tx_mux);
  LOG(NOTICE) << "TX A pgas: " << m_uTx->pga(0) << ", " << m_uTx->pga(1);
  writeLock.unlock();

  // RX on daughter A
  if (!skipRx) {
    writeLock.lock();
    m_uRx->_write_fpga_reg(FR_ATR_MASK_0  + 1*3,0);
    m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 1*3,0);
    m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 1*3,0);
    m_uRx->_write_fpga_reg(41,0);
    m_uRx->_write_fpga_reg(43,0);
    m_uRx->_write_oe(0,0,0xffff);
    m_uRx->_write_oe(0,(POWER_UP|RX2_RX1N|ENABLE), 0xffff);
    m_uRx->write_io(0, ENABLE | RX2_RX1N, ENABLE | RX2_RX1N | POWER_UP); /*
power up inverted */
    m_uRx->set_adc_buffer_bypass(0,true);
    m_uRx->set_adc_buffer_bypass(1,true);
    m_uRx->set_pga(0,m_uRx->pga_max()); // should be 20dB
    m_uRx->set_pga(1,m_uRx->pga_max());
    m_uRx->set_mux(rx_mux);
    writeLock.unlock();
    // FIXME -- This should be configurable.
    setRxGainA(47); //maxRxGain());
  }

  // TX on daughter B
    writeLock.lock();
  // power up and configure daughterboards
  m_uTx->_write_oe(1,0,0xffff);
  m_uTx->_write_oe(1,(POWER_UP|RX_TXN|ENABLE), 0xffff);
  m_uTx->write_io(1,ENABLE,(POWER_UP|RX_TXN|ENABLE)); /* POWER_UP inverted
*/
  m_uTx->_write_fpga_reg(FR_ATR_MASK_0 + 2*3,0);//RX_TXN|ENABLE);
  m_uTx->_write_fpga_reg(FR_ATR_TXVAL_0 + 2*3,0);//,0 |ENABLE);
  m_uTx->_write_fpga_reg(FR_ATR_RXVAL_0 + 2*3,0);//,RX_TXN|0);
  m_uTx->_write_fpga_reg(40,0);
  m_uTx->_write_fpga_reg(42,0);
  m_uTx->set_pga(2,m_uTx->pga_min()); // should be 20dB
  m_uTx->set_pga(3,m_uTx->pga_min());
  m_uTx->set_mux(tx_mux);
  LOG(INFO) << "TX B pgas: " << m_uTx->pga(2) << ", " << m_uTx->pga(3);
  writeLock.unlock();

  // RX on daughter B
  if (!skipRx) {
    writeLock.lock();
    m_uRx->_write_fpga_reg(FR_ATR_MASK_0  + 3*3,0);
    m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 3*3,0);
    m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 3*3,0);
    m_uRx->_write_fpga_reg(41,0);
    m_uRx->_write_fpga_reg(43,0);
    m_uRx->_write_oe(1,0,0xffff);
    m_uRx->_write_oe(1,(POWER_UP|RX2_RX1N|ENABLE), 0xffff);
    m_uRx->write_io(1, ENABLE | RX2_RX1N, ENABLE | RX2_RX1N | POWER_UP); /*
power up inverted */
    //m_uRx->_write_oe(1,(POWER_UP|RX_TXN|ENABLE), 0xffff);
    //m_uRx->write_io(1,(RX_TXN|ENABLE),(POWER_UP|RX_TXN|ENABLE)); /*
POWER_UP inverted */
    //m_uRx->write_io(1,0,RX2_RX1N); // using Tx/Rx/
    //m_uRx->write_io(1,RX2_RX1N,RX2_RX1N); // using Rx2
    m_uRx->set_adc_buffer_bypass(2,true);
    m_uRx->set_adc_buffer_bypass(3,true);
    m_uRx->set_pga(2,m_uRx->pga_max()); // should be 20dB
    m_uRx->set_pga(3,m_uRx->pga_max());
    m_uRx->set_mux(rx_mux);
    writeLock.unlock();
    // FIXME -- This should be configurable.
    setRxGainB(47); //maxRxGain());
  }

[Openbts-discuss] HELP: Sending 2 channels to USRP1 (OpenBTS application)

GSM L1-L3 stack with SIP network interfaces

[Openbts-discuss] HELP: Sending 2 channels to USRP1 (OpenBTS application)