From: <mad...@ke...> - 2008-03-31 17:18:32
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src/nv50_dac.c | 2 +- src/nv50_display.c | 20 +++++++++++++------- src/nv50_sor.c | 2 +- src/nv50reg.h | 22 ++++++++++++++++++---- 4 files changed, 33 insertions(+), 13 deletions(-) New commits: commit f54cea5662fdfc17762711a88892a27aed62f74c Author: Maarten Maathuis <mad...@gm...> Date: Mon Mar 31 19:17:50 2008 +0200 NV50: Some clock related cleanups + minor changes. diff --git a/src/nv50_dac.c b/src/nv50_dac.c index 1a9f88d..669e230 100644 --- a/src/nv50_dac.c +++ b/src/nv50_dac.c @@ -35,7 +35,7 @@ NV50DacSetPClk(xf86OutputPtr output, int pclk) { ScrnInfoPtr pScrn = output->scrn; NVPtr pNv = NVPTR(pScrn); - NVWrite(pNv, 0x00614280 + NV50OrOffset(output) * 0x800, 0); + NVWrite(pNv, NV50_DAC0_CLK_CTRL + NV50OrOffset(output) * 0x800, 0); } static void diff --git a/src/nv50_display.c b/src/nv50_display.c index 367d825..9112571 100644 --- a/src/nv50_display.c +++ b/src/nv50_display.c @@ -141,10 +141,15 @@ void NV50CrtcSetPClk(xf86CrtcPtr crtc) NVPtr pNv = NVPTR(pScrn); int lo_n, lo_m, hi_n, hi_m, p, i; /* These clocks are probably rerouted from the 0x4000 range to the 0x610000 range */ - CARD32 lo = NVRead(pNv, nv_crtc->head ? NV50_CRTC_VPLL2_A : NV50_CRTC_VPLL1_A); - CARD32 hi = NVRead(pNv, nv_crtc->head ? NV50_CRTC_VPLL2_B : NV50_CRTC_VPLL1_B); - - NVWrite(pNv, 0x00614100 + nv_crtc->head * 0x800, 0x10000610); + uint32_t lo = NVRead(pNv, nv_crtc->head ? NV50_CRTC1_VPLL_A : NV50_CRTC0_VPLL_A); + uint32_t hi = NVRead(pNv, nv_crtc->head ? NV50_CRTC1_VPLL_B : NV50_CRTC0_VPLL_B); + + /* bit0: The blob (and bios) seem to have this on (almost) always. + * I'm hoping this (experiment) will fix my image stability issues. + * bit9+10: These are off if a clock was never used. I think certain operations (restarting X) trigger this to go off as well. + * So for all we know, this may be *the* clock on/off indicator. + */ + NVWrite(pNv, NV50_CRTC0_CLK_CTRL1 + nv_crtc->head * 0x800, 0x10000611); lo &= 0xff00ff00; hi &= 0x8000ff00; @@ -152,9 +157,10 @@ void NV50CrtcSetPClk(xf86CrtcPtr crtc) lo |= (lo_m << 16) | lo_n; hi |= (p << 28) | (hi_m << 16) | hi_n; - NVWrite(pNv, nv_crtc->head ? NV50_CRTC_VPLL2_A : NV50_CRTC_VPLL1_A, lo); - NVWrite(pNv, nv_crtc->head ? NV50_CRTC_VPLL2_B : NV50_CRTC_VPLL1_B, hi); - NVWrite(pNv, 0x00614200 + nv_crtc->head * 0x800, 0); + NVWrite(pNv, nv_crtc->head ? NV50_CRTC1_VPLL_A : NV50_CRTC0_VPLL_A, lo); + NVWrite(pNv, nv_crtc->head ? NV50_CRTC1_VPLL_B : NV50_CRTC0_VPLL_B, hi); + /* There seem to be a few indicator bits, which are similar to the SOR_CTRL bits. */ + NVWrite(pNv, NV50_CRTC0_CLK_CTRL2 + nv_crtc->head * 0x800, 0); for(i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; diff --git a/src/nv50_sor.c b/src/nv50_sor.c index 0c3af76..829d2b2 100644 --- a/src/nv50_sor.c +++ b/src/nv50_sor.c @@ -40,7 +40,7 @@ NV50SorSetPClk(xf86OutputPtr output, int pclk) /* 0x70000 was a late addition to nv, mentioned as fixing tmds initialisation on certain gpu's. */ /* This *may* have solved my shaking image problem, but i am not sure. */ /* I presume it's some kind of clock setting, but what precisely i do not know. */ - NVWrite(pNv, 0x00614300 + NV50OrOffset(output) * 0x800, 0x70000 | ((pclk > limit) ? 0x101 : 0)); + NVWrite(pNv, NV50_SOR0_CLK_CTRL + NV50OrOffset(output) * 0x800, 0x70000 | ((pclk > limit) ? 0x101 : 0)); } static void diff --git a/src/nv50reg.h b/src/nv50reg.h index 4f15f42..213da37 100644 --- a/src/nv50reg.h +++ b/src/nv50reg.h @@ -51,11 +51,25 @@ #define NV50_CRTC0_RAM_AMOUNT 0x00610384 #define NV50_CRTC1_RAM_AMOUNT 0x00610784 +/* These CLK_CTRL names are a bit of a guess, i do have my reasons though. */ +#define NV50_CRTC0_CLK_CTRL1 0x00614100 /* These are probably redrirected from 0x4000 range (very similar regs to nv40, maybe different order) */ -#define NV50_CRTC_VPLL1_A 0x00614104 -#define NV50_CRTC_VPLL1_B 0x00614108 -#define NV50_CRTC_VPLL2_A 0x00614904 -#define NV50_CRTC_VPLL2_B 0x00614908 +#define NV50_CRTC0_VPLL_A 0x00614104 +#define NV50_CRTC0_VPLL_B 0x00614108 +#define NV50_CRTC0_CLK_CTRL2 0x00614200 + +#define NV50_DAC0_CLK_CTRL 0x00614280 +#define NV50_SOR0_CLK_CTRL 0x00614300 + +#define NV50_CRTC1_CLK_CTRL1 0x00614900 +#define NV50_CRTC1_VPLL_A 0x00614904 +#define NV50_CRTC1_VPLL_B 0x00614908 +#define NV50_CRTC1_CLK_CTRL2 0x00614A00 + +#define NV50_DAC1_CLK_CTRL 0x00614A80 +#define NV50_SOR1_CLK_CTRL 0x00614B00 + +#define NV50_DAC2_CLK_CTRL 0x00615280 #define NV50_DAC0_DPMS_CTRL 0x0061A004 #define NV50_DAC1_DPMS_CTRL 0x0061A804 |