From: Paolo N. <pne...@gm...> - 2010-12-29 14:29:22
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Hi Dietmar, In both cases I get vg#branch = 0.000000e+000, I am not able to reproduce your situation. Which release are you using ? P. On Dec 29, 2010, at 1:31 PM, Dietmar Warning wrote: > Hi Paolo, > > the both cases: > 1. > .model pmos pmos level = 14 version = 4.6.5 > * play around with one of this > +rbodymod = 1 > +rgatemod = 1 > > vb#branch = -2.00001e-013 > vd#branch = 1.000000e-013 > vg#branch = 1.665335e-016 > vs#branch = 1.000000e-013 > > > 2. > .model pmos pmos level = 14 version = 4.6.5 > * play around with one of this > *+rbodymod = 1 > *+rgatemod = 1 > > vb#branch = -2.00000e-013 > vd#branch = 1.000000e-013 > vg#branch = 0.000000e+000 > vs#branch = 1.000000e-013 > > I will come back later with further inverstigations. > Dietmar > > Am 29.12.2010 12:37, schrieb Paolo Nenzi: >> >> Hello Dietmar, >> >> I have tested your netlist with the 4 different settings ad do not see the gate current. I have attached an ODS file with the show output. I have checked the KCL and seems to be respected (dominated by drain current). >> >> Can you help me in spotting the problem ? >> >> Thanks, >> Paolo >> >> >> >> >> >> On Dec 29, 2010, at 11:29 AM, Dietmar Warning wrote: >> >>> Hi Paolo, >>> >>> I think it is clear a model problem. Try this (your simplified netlist): >>> --------------------------------- >>> pathology >>> *.options gmin=1e-018 abstol=1e-018 >>> .model pmos pmos level = 14 version = 4.6.5 >>> * play around with one of this >>> +rbodymod = 1 >>> +rgatemod = 1 >>> mp drain gate source body pmos w=45n l=45n >>> vd drain 0 0.0 >>> vg gate 0 0.1 >>> vs source 0 0.0 >>> vb body 0 0.1 >>> .control >>> op >>> show mp >>> print all >>> .endc >>> .end >>> --------------------------------- >>> If one of the internal additional networks (gate or body) is switched on a additional gate current appears and seems to flow in the model to ground. >>> Will try this with other simulators too. >>> >>> Dietmar >>> >>> >>> Am 29.12.2010 10:00, schrieb Paolo Nenzi: >>>> >>>> Ciao Dietmar, >>>> >>>> Looking again at the output, I do not see te e-18 current flowing, only the e-24 terms. May be we have some problem with voltage sources ? >>>> >>>> P. >>>> >>>> On Dec 28, 2010, at 11:33 PM, Paolo Nenzi wrote: >>>> >>>>> Sorry Dietmar, >>>>> >>>>> C does not stands for "C"urrent... >>>>> P. >>>>> >>>>> On Dec 28, 2010, at 11:16 PM, Paolo Nenzi wrote: >>>>> >>>>>> Dietmar, >>>>>> >>>>>> Please look at the output of the "show mp" commando when vdd=0.1. I see gate current contributions like cgg. Why they are not shown on vg#branch ? >>>>>> >>>>>> P. >>>>>> >>>>>> DBj_gidl_p >>>>>> >>>>>> .INCLUDE ..\..\..\..\..\Tecnologie\45nm_MGK_car2_gidlgisl.pm >>>>>> .OPTIONS GMIN=1e-023 ABSTOL=1e-23 >>>>>> >>>>>> *Definizione dei parametri >>>>>> .PARAM Lmin=45n >>>>>> .PARAM Wmin=45n >>>>>> .PARAM Ldiff=90n >>>>>> >>>>>> *Descrizione della cella >>>>>> Mp drain gate source body pmos W={Wmin} L={Lmin} AS={Wmin*Ldiff} AD={Wmin*Ldiff} PS={2*(Ldiff+Wmin)} PD={2*(Ldiff+Wmin)} >>>>>> Vd drain 0 0 >>>>>> Vg gate alim 0 >>>>>> Vs source 0 0 >>>>>> Vb body alim 0 >>>>>> Vdd alim 0 0 >>>>>> >>>>>> *Definizione del tipo di analisi >>>>>> .CONTROL >>>>>> let voltage=0 >>>>>> let Vddbasic=1.2 >>>>>> while voltage le Vddbasic >>>>>> let voltage = voltage + 0.05 >>>>>> alter Vdd = voltage >>>>>> dc TEMP 30 100 70 >>>>>> print abs(V(alim)) V(drain) V(gate) V(source) V(body) I(Vd) I(Vg) I(Vs) I(Vb) >>>>>> end >>>>>> .ENDC >>>>>> .END >>>>>> ngspice 2 -> alter vdd=0.1 >>>>>> ngspice 3 -> op >>>>>> Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 >>>>>> >>>>>> >>>>>> >>>>>> No. of Data Rows : 1 >>>>>> ngspice 4 -> show mp >>>>>> BSIM4: Berkeley Short Channel IGFET Model-4 >>>>>> device mp >>>>>> model pmos >>>>>> l 4.5e-08 >>>>>> w 4.5e-08 >>>>>> m 1 >>>>>> nf 1 >>>>>> sa 0 >>>>>> sb 0 >>>>>> sd 0 >>>>>> sca 0 >>>>>> scb 0 >>>>>> scc 0 >>>>>> sc 0 >>>>>> min 0 >>>>>> ad 4.05e-15 >>>>>> as 4.05e-15 >>>>>> pd 2.7e-07 >>>>>> ps 2.7e-07 >>>>>> nrd 1 >>>>>> nrs 1 >>>>>> off 0 >>>>>> rbdb 50 >>>>>> rbsb 50 >>>>>> rbpb 50 >>>>>> rbps 50 >>>>>> rbpd 50 >>>>>> delvto 0 >>>>>> xgw 0 >>>>>> ngcon 1 >>>>>> trnqsmod 0 >>>>>> acnqsmod 0 >>>>>> rbodymod 1 >>>>>> rgatemod 1 >>>>>> geomod 1 >>>>>> rgeomod 0 >>>>>> gmbs 0 >>>>>> gm 0 >>>>>> gds 1.18241e-09 >>>>>> vdsat 0.0477591 >>>>>> vth 0.239261 >>>>>> id 0 >>>>>> ibd -1e-24 >>>>>> ibs -1e-24 >>>>>> gbd 1e-23 >>>>>> gbs 1e-23 >>>>>> isub 0 >>>>>> igidl 0 >>>>>> igisl 0 >>>>>> igs 0 >>>>>> igd 0 >>>>>> igb 0 >>>>>> igcs 0 >>>>>> igcd 0 >>>>>> vbs -0.1 >>>>>> vgs -0.1 >>>>>> vds 0 >>>>>> cgg 3.22096e-18 >>>>>> cgs -3.7153e-21 >>>>>> cgd -1.25912e-22 >>>>>> cbg -3.22011e-18 >>>>>> cbd -4.93796e-22 >>>>>> cbs 3.38545e-21 >>>>>> cdg -4.21983e-22 >>>>>> cdd 4.2314e-22 >>>>>> cds 5.16405e-23 >>>>>> csg -4.21983e-22 >>>>>> csd 1.96567e-22 >>>>>> css 2.78214e-22 >>>>>> cgb -3.21712e-18 >>>>>> cdb -5.27983e-23 >>>>>> csb -5.27983e-23 >>>>>> cbb 3.21722e-18 >>>>>> capbd 3.39816e-17 >>>>>> capbs 3.39816e-17 >>>>>> qg 3.82088e-18 >>>>>> qb -3.82086e-18 >>>>>> qd -1.35946e-23 >>>>>> qs -1.35946e-23 >>>>>> qinv 1.64776e-22 >>>>>> qdef -0 >>>>>> gcrg 0 >>>>>> gtau 0 >>>>>> >>>>>> ngspice 5 -> print all >>>>>> alim = 1.000000e-01 >>>>>> body = 1.000000e-01 >>>>>> drain = 0.000000e+00 >>>>>> gate = 1.000000e-01 >>>>>> mp#body = 1.000000e-01 >>>>>> mp#dbody = 1.000000e-01 >>>>>> mp#gate = 0.000000e+00 >>>>>> mp#sbody = 1.000000e-01 >>>>>> source = 0.000000e+00 >>>>>> vb#branch = -1.30104e-18 >>>>>> vd#branch = 1.000000e-24 >>>>>> vdd#branch = -1.30104e-18 >>>>>> vg#branch = 0.000000e+00 >>>>>> vs#branch = 1.000000e-24 >>>>>> ngspice 6 -> >>>>>> >>>>>> >>>>>> On Dec 28, 2010, at 6:47 PM, Dietmar Warning wrote: >>>>>> >>>>>>> Paolo, >>>>>>> >>>>>>> look for jss, jssw (diode saturation current density) and alpha1 (impact ionization) >>>>>>> >>>>>>> Dietmar >>>>>>> >>>>>>> Am 28.12.2010 18:07, schrieb Paolo Nenzi: >>>>>>>> >>>>>>>> Hi Dietmar, >>>>>>>> >>>>>>>>>>> In the previous run I see the following inconsistencies: >>>>>>>>>>> >>>>>>>>>>> 1) mp#{body,dbody,gate,sbody} do not carry the correct current value. They come from CKTmkVolt in bsim4 models. >>>>>>>>> I think this is a misunderstanding about mp#xxx. This are voltages of the nodes in the 5 - body resistance network. Can you agree? >>>>>>>>> >>>>>>>> Right, the notation for current would be xxx#branch, and the values are consistent with voltages. >>>>>>>> >>>>>>>>>>> 2) i(vb) + i(vd) + i(vg) + i(vs) != 0 and, as you can see we have a body current much higher than source and drain currents. >>>>>>>>> I am not worried about the body current because we have two diodes with 0.1V across - but I am not in line that we have not adequate currents in vs and vd voltage sources. >>>>>>>> >>>>>>>> I am worried because KCL is not enforced but, I have to admit, the current level is unrealistically low. >>>>>>>> >>>>>>>>> That the current sum is not zero can also have a cause in the impact ionization current and gidl current components which are flowing to the primary body node. >>>>>>>> >>>>>>>> But they should come from somewhere otherwise we have charge creation/destruction in the model. Do you agree ? >>>>>>>> >>>>>>>>> Perhaps also we have 0V over drain-source. Then it would be a weakness in the model but not really a bug. >>>>>>>> >>>>>>>> I do not think anyone will use the model in such way, as I told you this is a test netlist for extracting leakage currents in mosfets. May be this is not the right way to procceed, an extrapolation should be better. >>>>>>>> >>>>>>>>> In your model each diode current is switched off - same for other components like impact ionization. So the assumption of numerical noise is more true. >>>>>>>> >>>>>>>> Ok for the noise, on the other issue (diode current and impact ionization) let me check the model list. They are the PTM models from ASU. >>>>>>>> >>>>>>>> Thanks, >>>>>>>> P. >>>>>>>> >>>>>>>> >>>>>>>>> >>>>>>>>>>> Any idea ? >>>>>>>>>>> >>>>>>>>>>> Ciao, >>>>>>>>>>> Paolo >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> ---------------------------------- Netlist ------------------------------------- >>>>>>>>>>> DBj_gidl_p >>>>>>>>>>> >>>>>>>>>>> .INCLUDE 45nm_MGK_car2_gidlgisl.pm >>>>>>>>>>> .OPTIONS GMIN=1e-023 ABSTOL=1e-23 >>>>>>>>>>> >>>>>>>>>>> *Parameter definition >>>>>>>>>>> .PARAM Lmin=45n >>>>>>>>>>> .PARAM Wmin=45n >>>>>>>>>>> .PARAM Ldiff=90n >>>>>>>>>>> >>>>>>>>>>> *Cell description >>>>>>>>>>> Mp drain gate source body pmos W={Wmin} L={Lmin} AS={Wmin*Ldiff} AD={Wmin*Ldiff} PS={2*(Ldiff+Wmin)} PD={2*(Ldiff+Wmin)} >>>>>>>>>>> Vd drain 0 0 >>>>>>>>>>> Vg gate 0 0.1 >>>>>>>>>>> Vs source 0 0 >>>>>>>>>>> Vb body 0 0.1 >>>>>>>>>>> *Vdd alim 0 0 >>>>>>>>>>> >>>>>>>>>>> .END >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> ------------------------------------------------------------------------------ >>>>>>>>>>> Lotusphere 2011 >>>>>>>>>>> Register now for Lotusphere 2011 and learn how >>>>>>>>>>> to connect the dots, take your collaborative environment >>>>>>>>>>> to the next level, and enter the era of Social Business. >>>>>>>>>>> http://p.sf.net/sfu/lotusphere-d2d >>>>>>>>>>> >>>>>>>>>>> _______________________________________________ >>>>>>>>>>> Ngspice-devel mailing list >>>>>>>>>>> Ngs...@li... >>>>>>>>>>> https://lists.sourceforge.net/lists/listinfo/ngspice-devel >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> ------------------------------------------------------------------------------ >>>>>>>>>> Forrester recently released a report on the Return on Investment (ROI) of >>>>>>>>>> Google Apps. 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------------------------------------------------------------------------------ > Learn how Oracle Real Application Clusters (RAC) One Node allows customers > to consolidate database storage, standardize their database environment, and, > should the need arise, upgrade to a full multi-node Oracle RAC database > without downtime or disruption > http://p.sf.net/sfu/oracle-sfdevnl_______________________________________________ > Ngspice-devel mailing list > Ngs...@li... > https://lists.sourceforge.net/lists/listinfo/ngspice-devel |