Menu
▾
▴
[nasm:HEAD] opflags: more int32_t -> opflags_t conversions
|
From: nasm-bot f. H. P. A. <hp...@zy...> - 2009-10-13 19:30:29
|
Commit-ID: f8563f7a987cd7b0d274d8895ece27fd475b319f Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=f8563f7a987cd7b0d274d8895ece27fd475b319f Author: H. Peter Anvin <hp...@zy...> AuthorDate: Tue, 13 Oct 2009 12:28:14 -0700 Committer: H. Peter Anvin <hp...@zy...> CommitDate: Tue, 13 Oct 2009 12:29:01 -0700 opflags: more int32_t -> opflags_t conversions Hopefully this should catch all of them... but please keep an eye out for any other uses of int32_t for the operand flags. Signed-off-by: H. Peter Anvin <hp...@zy...> --- assemble.c | 31 ++++---- disasm.c | 2 +- nasm.h | 197 +------------------------------------------------- opflags.h | 239 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ regs.pl | 2 +- tables.h | 9 +- 6 files changed, 262 insertions(+), 218 deletions(-) diff --git a/assemble.c b/assemble.c index 7ea5fb9..c329c3f 100644 --- a/assemble.c +++ b/assemble.c @@ -199,11 +199,11 @@ static enum match_result find_match(const struct itemplate **tempp, insn *instruction, int32_t segment, int64_t offset, int bits); static enum match_result matches(const struct itemplate *, insn *, int bits); -static int32_t regflag(const operand *); +static opflags_t regflag(const operand *); static int32_t regval(const operand *); -static int rexflags(int, int32_t, int); +static int rexflags(int, opflags_t, int); static int op_rexflags(const operand *, int); -static ea *process_ea(operand *, ea *, int, int, int, int32_t); +static ea *process_ea(operand *, ea *, int, int, int, opflags_t); static void add_asp(insn *, int); static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix) @@ -1137,7 +1137,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, { ea ea_data; int rfield; - int32_t rflags; + opflags_t rflags; struct operand *opy = &ins->oprs[op2]; ea_data.rex = 0; /* Ensure ea.REX is initially 0 */ @@ -1851,7 +1851,7 @@ static void gencode(int32_t segment, int64_t offset, int bits, { ea ea_data; int rfield; - int32_t rflags; + opflags_t rflags; uint8_t *p; int32_t s; enum out_type type; @@ -1940,7 +1940,7 @@ static void gencode(int32_t segment, int64_t offset, int bits, } } -static int32_t regflag(const operand * o) +static opflags_t regflag(const operand * o) { if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) { errfunc(ERR_PANIC, "invalid operand passed to regflag()"); @@ -1958,7 +1958,7 @@ static int32_t regval(const operand * o) static int op_rexflags(const operand * o, int mask) { - int32_t flags; + opflags_t flags; int val; if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) { @@ -1971,7 +1971,7 @@ static int op_rexflags(const operand * o, int mask) return rexflags(val, flags, mask); } -static int rexflags(int val, int32_t flags, int mask) +static int rexflags(int val, opflags_t flags, int mask) { int rex = 0; @@ -2225,7 +2225,7 @@ static enum match_result matches(const struct itemplate *itemp, } static ea *process_ea(operand * input, ea * output, int bits, - int addrbits, int rfield, int32_t rflags) + int addrbits, int rfield, opflags_t rflags) { bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN); @@ -2236,7 +2236,7 @@ static ea *process_ea(operand * input, ea * output, int bits, if (is_class(REGISTER, input->type)) { /* register direct */ int i; - int32_t f; + opflags_t f; if (input->basereg < EXPR_REG_START /* Verify as Register */ || input->basereg >= REG_ENUM_LIMIT) @@ -2276,9 +2276,8 @@ static ea *process_ea(operand * input, ea * output, int bits, int i = input->indexreg, b = input->basereg, s = input->scale; int32_t o = input->offset, seg = input->segment; int hb = input->hintbase, ht = input->hinttype; - int t; - int it, bt; - int32_t ix, bx; /* register flags */ + int t, it, bt; /* register numbers */ + opflags_t x, ix, bx; /* register flags */ if (s == 0) i = -1; /* make this easy, at least */ @@ -2336,7 +2335,7 @@ static ea *process_ea(operand * input, ea * output, int bits, || (hb == i && ht == EAH_MAKEBASE))) { /* swap if hints say so */ t = bt, bt = it, it = t; - t = bx, bx = ix, ix = t; + x = bx, bx = ix, ix = x; } if (bt == it) /* convert EAX+2*EAX to 3*EAX */ bt = -1, bx = 0, s++; @@ -2355,7 +2354,7 @@ static ea *process_ea(operand * input, ea * output, int bits, if (s == 1 && it == REG_NUM_ESP) { /* swap ESP into base if scale is 1 */ t = it, it = bt, bt = t; - t = ix, ix = bx, bx = t; + x = ix, ix = bx, bx = x; } if (it == REG_NUM_ESP || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1)) @@ -2559,7 +2558,7 @@ static void add_asp(insn *ins, int addrbits) for (j = 0; j < ins->operands; j++) { if (!(MEMORY & ~ins->oprs[j].type)) { - int32_t i, b; + opflags_t i, b; /* Verify as Register */ if (ins->oprs[j].indexreg < EXPR_REG_START diff --git a/disasm.c b/disasm.c index 6a2554b..ede485a 100644 --- a/disasm.c +++ b/disasm.c @@ -110,7 +110,7 @@ static uint64_t getu64(uint8_t *data) #define gets64(x) ((int64_t)getu64(x)) /* Important: regval must already have been adjusted for rex extensions */ -static enum reg_enum whichreg(int32_t regflags, int regval, int rex) +static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) { if (!(regflags & (REGISTER|REGMEM))) return 0; /* Registers not permissible?! */ diff --git a/nasm.h b/nasm.h index 2982101..5d5aae7 100644 --- a/nasm.h +++ b/nasm.h @@ -46,6 +46,7 @@ #include "preproc.h" #include "insnsi.h" /* For enum opcode */ #include "directives.h" /* For enum directive */ +#include "opflags.h" #define NO_SEG -1L /* null segment value */ #define SEG_ABS 0x40000000L /* mask for far-absolute segments */ @@ -416,202 +417,6 @@ enum { * ----------------------------------------------------------- */ -/* - * Here we define the operand types. These are implemented as bit - * masks, since some are subsets of others; e.g. AX in a MOV - * instruction is a special operand type, whereas AX in other - * contexts is just another 16-bit register. (Also, consider CL in - * shift instructions, DX in OUT, etc.) - * - * The basic concept here is that - * (class & ~operand) == 0 - * - * if and only if "operand" belongs to class type "class". - * - * The bits are assigned as follows: - * - * Bits 0-7, 23, 29: sizes - * 0: 8 bits (BYTE) - * 1: 16 bits (WORD) - * 2: 32 bits (DWORD) - * 3: 64 bits (QWORD) - * 4: 80 bits (TWORD) - * 5: FAR - * 6: NEAR - * 7: SHORT - * 23: 256 bits (YWORD) - * 29: 128 bits (OWORD) - * - * Bits 8-11 modifiers - * 8: TO - * 9: COLON - * 10: STRICT - * 11: (reserved) - * - * Bits 12-15: type of operand - * 12: REGISTER - * 13: IMMEDIATE - * 14: MEMORY (always has REGMEM attribute as well) - * 15: REGMEM (valid EA operand) - * - * Bits 16-19, 28: subclasses - * With REG_CDT: - * 16: REG_CREG (CRx) - * 17: REG_DREG (DRx) - * 18: REG_TREG (TRx) - - * With REG_GPR: - * 16: REG_ACCUM (AL, AX, EAX, RAX) - * 17: REG_COUNT (CL, CX, ECX, RCX) - * 18: REG_DATA (DL, DX, EDX, RDX) - * 19: REG_HIGH (AH, CH, DH, BH) - * 28: REG_NOTACC (not REG_ACCUM) - * - * With REG_SREG: - * 16: REG_CS - * 17: REG_DESS (DS, ES, SS) - * 18: REG_FSGS - * 19: REG_SEG67 - * - * With FPUREG: - * 16: FPU0 - * - * With XMMREG: - * 16: XMM0 - * - * With YMMREG: - * 16: YMM0 - * - * With MEMORY: - * 16: MEM_OFFS (this is a simple offset) - * 17: IP_REL (IP-relative offset) - * - * With IMMEDIATE: - * 16: UNITY (1) - * 17: BYTENESS16 (-128..127) - * 18: BYTENESS32 (-128..127) - * 19: BYTENESS64 (-128..127) - * - * Bits 20-22, 24-27: register classes - * 20: REG_CDT (CRx, DRx, TRx) - * 21: RM_GPR (REG_GPR) (integer register) - * 22: REG_SREG - * 24: FPUREG - * 25: RM_MMX (MMXREG) - * 26: RM_XMM (XMMREG) - * 27: RM_YMM (YMMREG) - * - * Bit 31 is currently unallocated. - * - * 30: SAME_AS - * Special flag only used in instruction patterns; means this operand - * has to be identical to another operand. Currently only supported - * for registers. - */ - -typedef uint32_t opflags_t; - -/* Size, and other attributes, of the operand */ -#define BITS8 0x00000001U -#define BITS16 0x00000002U -#define BITS32 0x00000004U -#define BITS64 0x00000008U /* x64 and FPU only */ -#define BITS80 0x00000010U /* FPU only */ -#define BITS128 0x20000000U -#define BITS256 0x00800000U -#define FAR 0x00000020U /* grotty: this means 16:16 or */ - /* 16:32, like in CALL/JMP */ -#define NEAR 0x00000040U -#define SHORT 0x00000080U /* and this means what it says :) */ - -#define SIZE_MASK 0x208000FFU /* all the size attributes */ - -/* Modifiers */ -#define MODIFIER_MASK 0x00000f00U -#define TO 0x00000100U /* reverse effect in FADD, FSUB &c */ -#define COLON 0x00000200U /* operand is followed by a colon */ -#define STRICT 0x00000400U /* do not optimize this operand */ - -/* Type of operand: memory reference, register, etc. */ -#define OPTYPE_MASK 0x0000f000U -#define REGISTER 0x00001000U /* register number in 'basereg' */ -#define IMMEDIATE 0x00002000U -#define MEMORY 0x0000c000U -#define REGMEM 0x00008000U /* for r/m, ie EA, operands */ - -#define is_class(class, op) (!((opflags_t)(class) & ~(opflags_t)(op))) - -/* Register classes */ -#define REG_EA 0x00009000U /* 'normal' reg, qualifies as EA */ -#define RM_GPR 0x00208000U /* integer operand */ -#define REG_GPR 0x00209000U /* integer register */ -#define REG8 0x00209001U /* 8-bit GPR */ -#define REG16 0x00209002U /* 16-bit GPR */ -#define REG32 0x00209004U /* 32-bit GPR */ -#define REG64 0x00209008U /* 64-bit GPR */ -#define FPUREG 0x01001000U /* floating point stack registers */ -#define FPU0 0x01011000U /* FPU stack register zero */ -#define RM_MMX 0x02008000U /* MMX operand */ -#define MMXREG 0x02009000U /* MMX register */ -#define RM_XMM 0x04008000U /* XMM (SSE) operand */ -#define XMMREG 0x04009000U /* XMM (SSE) register */ -#define XMM0 0x04019000U /* XMM register zero */ -#define RM_YMM 0x08008000U /* YMM (AVX) operand */ -#define YMMREG 0x08009000U /* YMM (AVX) register */ -#define YMM0 0x08019000U /* YMM register zero */ -#define REG_CDT 0x00101004U /* CRn, DRn and TRn */ -#define REG_CREG 0x00111004U /* CRn */ -#define REG_DREG 0x00121004U /* DRn */ -#define REG_TREG 0x00141004U /* TRn */ -#define REG_SREG 0x00401002U /* any segment register */ -#define REG_CS 0x00411002U /* CS */ -#define REG_DESS 0x00421002U /* DS, ES, SS */ -#define REG_FSGS 0x00441002U /* FS, GS */ -#define REG_SEG67 0x00481002U /* Unimplemented segment registers */ - -#define REG_RIP 0x00801008U /* RIP relative addressing */ -#define REG_EIP 0x00801004U /* EIP relative addressing */ - -/* Special GPRs */ -#define REG_SMASK 0x100f0000U /* a mask for the following */ -#define REG_ACCUM 0x00219000U /* accumulator: AL, AX, EAX, RAX */ -#define REG_AL 0x00219001U -#define REG_AX 0x00219002U -#define REG_EAX 0x00219004U -#define REG_RAX 0x00219008U -#define REG_COUNT 0x10229000U /* counter: CL, CX, ECX, RCX */ -#define REG_CL 0x10229001U -#define REG_CX 0x10229002U -#define REG_ECX 0x10229004U -#define REG_RCX 0x10229008U -#define REG_DL 0x10249001U /* data: DL, DX, EDX, RDX */ -#define REG_DX 0x10249002U -#define REG_EDX 0x10249004U -#define REG_RDX 0x10249008U -#define REG_HIGH 0x10289001U /* high regs: AH, CH, DH, BH */ -#define REG_NOTACC 0x10000000U /* non-accumulator register */ -#define REG8NA 0x10209001U /* 8-bit non-acc GPR */ -#define REG16NA 0x10209002U /* 16-bit non-acc GPR */ -#define REG32NA 0x10209004U /* 32-bit non-acc GPR */ -#define REG64NA 0x10209008U /* 64-bit non-acc GPR */ - -/* special types of EAs */ -#define MEM_OFFS 0x0001c000U /* simple [address] offset - absolute! */ -#define IP_REL 0x0002c000U /* IP-relative offset */ - -/* memory which matches any type of r/m operand */ -#define MEMORY_ANY (MEMORY|RM_GPR|RM_MMX|RM_XMM|RM_YMM) - -/* special type of immediate operand */ -#define UNITY 0x00012000U /* for shift/rotate instructions */ -#define SBYTE16 0x00022000U /* for op r16,immediate instrs. */ -#define SBYTE32 0x00042000U /* for op r32,immediate instrs. */ -#define SBYTE64 0x00082000U /* for op r64,immediate instrs. */ -#define BYTENESS 0x000e0000U /* for testing for byteness */ - -/* special flags */ -#define SAME_AS 0x40000000U - /* Register names automatically generated from regs.dat */ #include "regs.h" diff --git a/opflags.h b/opflags.h new file mode 100644 index 0000000..b491244 --- /dev/null +++ b/opflags.h @@ -0,0 +1,239 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * opflags.h - operand flags + */ + +#ifndef NASM_OPFLAGS_H +#define NASM_OPFLAGS_H + +#include "compiler.h" + +/* + * Here we define the operand types. These are implemented as bit + * masks, since some are subsets of others; e.g. AX in a MOV + * instruction is a special operand type, whereas AX in other + * contexts is just another 16-bit register. (Also, consider CL in + * shift instructions, DX in OUT, etc.) + * + * The basic concept here is that + * (class & ~operand) == 0 + * + * if and only if "operand" belongs to class type "class". + * + * The bits are assigned as follows: + * + * Bits 0-7, 23, 29: sizes + * 0: 8 bits (BYTE) + * 1: 16 bits (WORD) + * 2: 32 bits (DWORD) + * 3: 64 bits (QWORD) + * 4: 80 bits (TWORD) + * 5: FAR + * 6: NEAR + * 7: SHORT + * 23: 256 bits (YWORD) + * 29: 128 bits (OWORD) + * + * Bits 8-11 modifiers + * 8: TO + * 9: COLON + * 10: STRICT + * 11: (reserved) + * + * Bits 12-15: type of operand + * 12: REGISTER + * 13: IMMEDIATE + * 14: MEMORY (always has REGMEM attribute as well) + * 15: REGMEM (valid EA operand) + * + * Bits 16-19, 28: subclasses + * With REG_CDT: + * 16: REG_CREG (CRx) + * 17: REG_DREG (DRx) + * 18: REG_TREG (TRx) + + * With REG_GPR: + * 16: REG_ACCUM (AL, AX, EAX, RAX) + * 17: REG_COUNT (CL, CX, ECX, RCX) + * 18: REG_DATA (DL, DX, EDX, RDX) + * 19: REG_HIGH (AH, CH, DH, BH) + * 28: REG_NOTACC (not REG_ACCUM) + * + * With REG_SREG: + * 16: REG_CS + * 17: REG_DESS (DS, ES, SS) + * 18: REG_FSGS + * 19: REG_SEG67 + * + * With FPUREG: + * 16: FPU0 + * + * With XMMREG: + * 16: XMM0 + * + * With YMMREG: + * 16: YMM0 + * + * With MEMORY: + * 16: MEM_OFFS (this is a simple offset) + * 17: IP_REL (IP-relative offset) + * + * With IMMEDIATE: + * 16: UNITY (1) + * 17: BYTENESS16 (-128..127) + * 18: BYTENESS32 (-128..127) + * 19: BYTENESS64 (-128..127) + * + * Bits 20-22, 24-27: register classes + * 20: REG_CDT (CRx, DRx, TRx) + * 21: RM_GPR (REG_GPR) (integer register) + * 22: REG_SREG + * 24: FPUREG + * 25: RM_MMX (MMXREG) + * 26: RM_XMM (XMMREG) + * 27: RM_YMM (YMMREG) + * + * Bit 31 is currently unallocated. + * + * 30: SAME_AS + * Special flag only used in instruction patterns; means this operand + * has to be identical to another operand. Currently only supported + * for registers. + */ + +typedef uint32_t opflags_t; + +/* Size, and other attributes, of the operand */ +#define BITS8 0x00000001U +#define BITS16 0x00000002U +#define BITS32 0x00000004U +#define BITS64 0x00000008U /* x64 and FPU only */ +#define BITS80 0x00000010U /* FPU only */ +#define BITS128 0x20000000U +#define BITS256 0x00800000U +#define FAR 0x00000020U /* grotty: this means 16:16 or */ + /* 16:32, like in CALL/JMP */ +#define NEAR 0x00000040U +#define SHORT 0x00000080U /* and this means what it says :) */ + +#define SIZE_MASK 0x208000FFU /* all the size attributes */ + +/* Modifiers */ +#define MODIFIER_MASK 0x00000f00U +#define TO 0x00000100U /* reverse effect in FADD, FSUB &c */ +#define COLON 0x00000200U /* operand is followed by a colon */ +#define STRICT 0x00000400U /* do not optimize this operand */ + +/* Type of operand: memory reference, register, etc. */ +#define OPTYPE_MASK 0x0000f000U +#define REGISTER 0x00001000U /* register number in 'basereg' */ +#define IMMEDIATE 0x00002000U +#define MEMORY 0x0000c000U +#define REGMEM 0x00008000U /* for r/m, ie EA, operands */ + +#define is_class(class, op) (!((opflags_t)(class) & ~(opflags_t)(op))) + +/* Register classes */ +#define REG_EA 0x00009000U /* 'normal' reg, qualifies as EA */ +#define RM_GPR 0x00208000U /* integer operand */ +#define REG_GPR 0x00209000U /* integer register */ +#define REG8 0x00209001U /* 8-bit GPR */ +#define REG16 0x00209002U /* 16-bit GPR */ +#define REG32 0x00209004U /* 32-bit GPR */ +#define REG64 0x00209008U /* 64-bit GPR */ +#define FPUREG 0x01001000U /* floating point stack registers */ +#define FPU0 0x01011000U /* FPU stack register zero */ +#define RM_MMX 0x02008000U /* MMX operand */ +#define MMXREG 0x02009000U /* MMX register */ +#define RM_XMM 0x04008000U /* XMM (SSE) operand */ +#define XMMREG 0x04009000U /* XMM (SSE) register */ +#define XMM0 0x04019000U /* XMM register zero */ +#define RM_YMM 0x08008000U /* YMM (AVX) operand */ +#define YMMREG 0x08009000U /* YMM (AVX) register */ +#define YMM0 0x08019000U /* YMM register zero */ +#define REG_CDT 0x00101004U /* CRn, DRn and TRn */ +#define REG_CREG 0x00111004U /* CRn */ +#define REG_DREG 0x00121004U /* DRn */ +#define REG_TREG 0x00141004U /* TRn */ +#define REG_SREG 0x00401002U /* any segment register */ +#define REG_CS 0x00411002U /* CS */ +#define REG_DESS 0x00421002U /* DS, ES, SS */ +#define REG_FSGS 0x00441002U /* FS, GS */ +#define REG_SEG67 0x00481002U /* Unimplemented segment registers */ + +#define REG_RIP 0x00801008U /* RIP relative addressing */ +#define REG_EIP 0x00801004U /* EIP relative addressing */ + +/* Special GPRs */ +#define REG_SMASK 0x100f0000U /* a mask for the following */ +#define REG_ACCUM 0x00219000U /* accumulator: AL, AX, EAX, RAX */ +#define REG_AL 0x00219001U +#define REG_AX 0x00219002U +#define REG_EAX 0x00219004U +#define REG_RAX 0x00219008U +#define REG_COUNT 0x10229000U /* counter: CL, CX, ECX, RCX */ +#define REG_CL 0x10229001U +#define REG_CX 0x10229002U +#define REG_ECX 0x10229004U +#define REG_RCX 0x10229008U +#define REG_DL 0x10249001U /* data: DL, DX, EDX, RDX */ +#define REG_DX 0x10249002U +#define REG_EDX 0x10249004U +#define REG_RDX 0x10249008U +#define REG_HIGH 0x10289001U /* high regs: AH, CH, DH, BH */ +#define REG_NOTACC 0x10000000U /* non-accumulator register */ +#define REG8NA 0x10209001U /* 8-bit non-acc GPR */ +#define REG16NA 0x10209002U /* 16-bit non-acc GPR */ +#define REG32NA 0x10209004U /* 32-bit non-acc GPR */ +#define REG64NA 0x10209008U /* 64-bit non-acc GPR */ + +/* special types of EAs */ +#define MEM_OFFS 0x0001c000U /* simple [address] offset - absolute! */ +#define IP_REL 0x0002c000U /* IP-relative offset */ + +/* memory which matches any type of r/m operand */ +#define MEMORY_ANY (MEMORY|RM_GPR|RM_MMX|RM_XMM|RM_YMM) + +/* special type of immediate operand */ +#define UNITY 0x00012000U /* for shift/rotate instructions */ +#define SBYTE16 0x00022000U /* for op r16,immediate instrs. */ +#define SBYTE32 0x00042000U /* for op r32,immediate instrs. */ +#define SBYTE64 0x00082000U /* for op r64,immediate instrs. */ +#define BYTENESS 0x000e0000U /* for testing for byteness */ + +/* special flags */ +#define SAME_AS 0x40000000U + +#endif /* NASM_OPFLAGS_H */ diff --git a/regs.pl b/regs.pl index bfce1d0..82c4829 100755 --- a/regs.pl +++ b/regs.pl @@ -151,7 +151,7 @@ if ( $fmt eq 'h' ) { print "/* automatically generated from $file - do not edit */\n\n"; print "#include \"tables.h\"\n"; print "#include \"nasm.h\"\n\n"; - print "const int32_t nasm_reg_flags[] = {\n"; + print "const opflags_t nasm_reg_flags[] = {\n"; printf " 0,\n"; # Dummy entry for 0 foreach $reg ( sort(keys(%regs)) ) { # Print the class of the register diff --git a/tables.h b/tables.h index 284f046..e6f84cb 100644 --- a/tables.h +++ b/tables.h @@ -37,12 +37,13 @@ * Declarations for auto-generated tables */ -#ifndef TABLES_H -#define TABLES_H +#ifndef NASM_TABLES_H +#define NASM_TABLES_H #include "compiler.h" #include <inttypes.h> #include "insnsi.h" /* For enum opcode */ +#include "opflags.h" /* For opflags_t */ /* --- From standard.mac via macros.pl: --- */ @@ -61,8 +62,8 @@ extern const char * const nasm_insn_names[]; /* regs.c */ extern const char * const nasm_reg_names[]; /* regflags.c */ -extern const int32_t nasm_reg_flags[]; +extern const opflags_t nasm_reg_flags[]; /* regvals.c */ extern const int nasm_regvals[]; -#endif /* TABLES_H */ +#endif /* NASM_TABLES_H */ |