Re: [Nasm-devel] start implementing XOP

[Cyrill G. <gor...@gm...>]

Thanks a lot for comments, Peter!
I'll continue after read a bit of nasm sourses and docs as well (a few
days probably).

(sorry for top posting)

On 5/12/09, H. Peter Anvin <hp...@zy...> wrote:
> Hi Cyrill!
>
> First of all, thank you for doing this.
>
> Cyrill Gorcunov wrote:
>> +VPHADDUBD	ymmreg,ymmrm			[rm:	xop.128.m9 d2 /r]			AMD,SSE5,SO
>> +VPHADDUBQ	xmmreg,xmmrm			[rm:	xop.128.m9 d3 /r]			AMD,SSE5,SO
>> +VPHADDUBW	xmmreg,xmmrm			[rm:	xop.128.m9 d1 /r]			AMD,SSE5,SO
>
> VPHADDUBD being ymmreg has to be a bug in the spec...
>
>> +;
>> +; FIXME: should it be "db" instead of "d8" (like "cb" has)?
>> +VPHADDUDQ	xmmreg,xmmrm			[rm:	xop.128.m9 d8 /r]			AMD,SSE5,SO
>> +VPHADDUWD	xmmreg,xmmrm			[rm:	xop.128.m9 d6 /r]			AMD,SSE5,SO
>> +VPHADDUWQ	xmmreg,xmmrm			[rm:	xop.128.m9 d7 /r]			AMD,SSE5,SO
>> +VPHADDWD	ymmreg,ymmrm			[rm:	xop.128.m9 c6 /r]			AMD,SSE5,SO
>
> Same with WPHADDWD here...
>
>> +VPMACSDD	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 9e /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSDQH	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 9f /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSDQL	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 97 /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSSDD	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 8e /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSSDQH	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 8f /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSSDQL	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 87 /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSSWD	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 86 /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSSWW	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 85 /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSWD	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 96 /r
>> /is4]		AMD,SSE5,SO
>> +VPMACSWW	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 95 /r
>> /is4]		AMD,SSE5,SO
>> +VPMADCSSWD	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 a6 /r
>> /is4]		AMD,SSE5,SO
>> +VPMADCSWD	xmmreg,xmmrm,xmmreg		[r+vms:	xop.nds.128.m8 b6 /r
>> /is4]		AMD,SSE5,SO
>
> Looks right for the "relaxed" forms (three-operand); it also needs the
> four-operand forms:
>
> VPMACSDD	xmmreg,xmmreg,xmmrm,xmmreg
> 	[rvms:	xop.nds.128.m8 9e /r /is4]		AMD,SSE5,SO
>
> Those go before the relaxed forms, since the four-operand form is the
> documented one (and therefore is what the disassembler should see.)
>
>> +VPROTB		xmmreg,xmmreg,xmmrm		[r+vm:	xop.nds.128.m9.w1 90 /r]		AMD,SSE5,SO
>
> That should be rvm: not r+vm: (three operands on the left, not two
> operands... "r+v" only corresponds to a single operand.)
>
>> +VPROTB		xmmreg,xmmreg,xmmrm		[r+vm:	xop.nds.128.m9.w1 90 /r]		AMD,SSE5,SO
>
> That should presumably be "xmmreg,xmmrm,xmmreg" and "rmv:".
>
> The only relaxed form that makes sense would be:
>
> VPROTB			xmmreg,xmmrm			[r+vm:	xop.nds.128.w1 90 /r]
>
>> +VPROTB		xmmreg,imm8			[ri:	xop.128.m8 c0 ib]			AMD,SSE5,SO
>
> Per the docs, there are three operands, which we can also do a
> two-operand relaxed form of:
>
> VPROTB			xmmreg,xmmreg,imm
> 	[rmi:	xop.128.m8 c0 ib]
> VPROTB			xmmreg,imm
> 	[r+mi:	xop.128.m8 c0 ib]
>
> 	-hpa
>
> --
> H. Peter Anvin, Intel Open Source Technology Center
> I work for Intel.  I don't speak on their behalf.
>
>