Re: [myhdl-list] No proper edge value test

[Christopher F. <chr...@gm...>]

On 7/18/2012 6:24 AM, Jan Decaluwe wrote:
> On 07/18/2012 05:05 AM, Christopher Felton wrote:
>> With the latest 0.8dev code the following will cause
>> a "No proper edge value test"
>>
>>       def testm(clock, reset, out):
>>           @always(clock.posedge, reset.negedge)
>>           def hdl():
>>               if not reset:
>>                   out.next = 0
>>               else:
>>                   out.next = out ^ 0x55
>>
>>           return hdl
>>
>>       def convert():
>>           clock = Signal(False)
>>           reset = Signal(False)
>>           out   = Signal(intbv(0)[8:])
>>           toVerilog(testm, clock, reset, out)
>>           toVHDL(testm, clock, reset, out)
>>
>>
>> Is this expected behavior?  This could possibly break
>> existing code.
>
> Don't think so - same in 0.7.
>
> Yes, I would call it expected behavior. A reset should
> check on a value - giving it a logical interpretation
> can only lead to confusion. (As here, where 'not reset'
> checks for an active reset.)
>

Ahh, I didn't describe the observed issue correctly.  It
is the difference between toVerilog and toVHDL.  Not a
difference between revisions, toVerilog will accept the
above toVHDL will error.

And both will accept

    ...
    if reset
    ...

In the past I had only used toVerilog and when I added
a toVHDL, I mistakenly thought it might have been a
change in behavior due to recent changes.

Regards,
Chris