Re: [myhdl-list] Reset functionality "synthesis"
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From: Jan D. <ja...@ja...> - 2012-07-06 10:38:57
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On 07/05/2012 06:20 PM, Tom Dillon wrote: > > In my experience, sometimes you want the registers in the DSP48 block > and other times not. Ok. > Again though, nothing we are talking about will box you into a certain > type of reset Exactly. > I think we are just talking about the default cases? Actually we are considering whether we should have default case or not for a ResetSignal. I'm convinced now that having no defaults at all is the best option. > There I times when I want no reset, so shift registers can use the > distributed memory in Xilinx FPGAs, but as long as I can control that > from the logic description I am OK. Ok. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |