Re: [myhdl-list] MEP guidelines
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jandecaluwe
From: Jan D. <ja...@ja...> - 2011-05-18 16:14:49
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Guenter: I notice no objections, and for me this is fine also. I propose to add this info, so that the rules are explicitly clear, and because some MEPs need maintenance. Jan On 05/10/2011 04:46 PM, Günter Dannoritzer wrote: > On 10.05.2011 09:59, Jan Decaluwe wrote: >> On 05/06/2011 05:03 PM, Günter Dannoritzer wrote: >>> Hi, >>> >>> I would like to suggest, adding some guidelines about the MEP process. >>> Seeing that the text of an already implemented MEP got changed, I think >>> it would be helpfull to have some guidelines how the MEP process is >>> intended. >> >> Good idea. Looking at your draft however: without BDFL powers (for me) >> it's a no-go as for as I'm concerned, and also unworkable in practice >> I believe. > > Yes, I have been thinking about that. Referring to your other post, I > also agree, not to make this process too complicated. > > My suggestion would be, that a MEP can only achieve the final state by > approval of you. That keeps the process simple and not add additional > states like 'Rejected'. > > I updated the draft and added your case in point to it. So the updated > version of the guidelines would be like this: > > --------- > MEP stands for MyHDL Enhancement Proposal. A MEP is a design document > providing information to the MyHDL community, or describing a new > feature for MyHDL. The MEP should provide a concise technical > specification of the feature and a rationale for the feature. > > We intend MEPs to be the primary mechanisms for proposing new features, > for collecting community input on an issue, and for documenting the > design decisions that have gone into MyHDL. The MEP author is > responsible for building consensus within the community and documenting > dissenting opinions. > > MEPs are maintained on the MyHDL wiki page. The page history resembles > the development history of the document. > > Main responsibility of a MEP lies with its author. Before opening a new > MEP, its idea should be discussed on the MyHDL mailing list. > > In the development phase, the MEP gets the status "Draft" assigned. > Fully developed and provided with a functional implementation, the MEP > can get the status "Final", documenting that the content of the MEP is > ready to be implemented into MyHDL. > > The right to change the status of a MEP from "Draft" to "Final" belongs > exclusively to Jan Decaluwe. > > Once the MEP has the status "Final" and its content got added to the > source code, the MyHDL version will be added to the MEP document. From > this time on, the text of the document will be frozen. A "Final" MEP > should not be changed, except for spelling mistakes or language > corrections from a neutral proofreader. It is intended to document the > MyHDL development history for experts. The MyHDL language documentation > for users is in the manuals. > > In case the functionality described in a MEP needs to be altered or > extended, a new MEP shall be created, describing the new desired > implementation. The new MEP will live through the same steps as the MEP > process describes. The new MEP should cross reference the MEP its > implementation is based on. > > In case the new MEP will replace an implementation of an existing MEP, > the old MEP will achieve the status "Deprecated" as soon as the new MEP > achieves the status "Final". Both MEPs should cross reference each other. > > ------------ > > Hope this did not become too complicated :) > > If there are no objections to these guidelines, I will put them on the > wiki page. > > Cheers, Guenter > > ------------------------------------------------------------------------------ > Achieve unprecedented app performance and reliability > What every C/C++ and Fortran developer should know. > Learn how Intel has extended the reach of its next-generation tools > to help boost performance applications - inlcuding clusters. > http://p.sf.net/sfu/intel-dev2devmay -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |