Re: [myhdl-list] Support for z and x signal levels in Verilog?

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> I have searched the documentation and the wiki but was unable to find 
> anything in regards to whether or not MyHDL supports Verilog's high 
> impedance and undefined signal levels?
> 
> Does anyone know if there is a way to do this?

1) Modelling
I never quite liked X. It was originally invented for gate level
simulation, and even there I always thought it creates more problems
than it solves. I think RTL modelling and beyond (which is were
MyHDL is positioned) can do without it.

That having said, Python has a "high-level" object for undefined values,
None. It is the default value of Signals and intbv's and could be used 
for modeling.

None is also proposed to represent tristate values in the
following mep:

http://www.myhdl.org/doku.php/meps:mep-103

The distribution contains an experimental implementation of this
for modeling, but it is undocumented in the manual.

2) Conversion to Verilog
At this moment, the convertor neither writes X nor Z. I don't
think it will ever write X. For Z, it could support the mep
referenced above at some point.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org