[Madwifi-cvs] revision 1858 committed
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[Madwifi-cvs] revision 1858 committed
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From: Nick K. <svn...@ma...> - 2006-12-14 19:22:11
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Project : madwifi
Revision : 1858
Author : mickflemm (Nick Kossifidis)
Date : 2006-12-14 20:22:00 +0100 (Thu, 14 Dec 2006)
Log Message :
Update openhal's code.
Affected Files:
* branches/dadwifi-openhal/openhal/README updated
* branches/dadwifi-openhal/openhal/ah_devid.h updated
* branches/dadwifi-openhal/openhal/ar5210.c updated
* branches/dadwifi-openhal/openhal/ar5211.c updated
* branches/dadwifi-openhal/openhal/ar5212.c updated
* branches/dadwifi-openhal/openhal/ar5xxx.c updated
* branches/dadwifi-openhal/openhal/ar5xxx.h updated
Modified: branches/dadwifi-openhal/openhal/README
===================================================================
--- branches/dadwifi-openhal/openhal/README 2006-12-14 19:00:50 UTC (rev 1857)
+++ branches/dadwifi-openhal/openhal/README 2006-12-14 19:22:00 UTC (rev 1858)
@@ -1,4 +1,4 @@
-Linux OpenHAL 20062302
+Linux OpenHAL 20061412
======================
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\
* This is a port of the ar5k hal for atheros device drivers that is *
@@ -114,4 +114,3 @@
* Lot's of tests and fixes.
* Make it combatible with newer versions of MadWiFi (after the merge).
* Test 5210/5211 code.
-
Modified: branches/dadwifi-openhal/openhal/ah_devid.h
===================================================================
--- branches/dadwifi-openhal/openhal/ah_devid.h 2006-12-14 19:00:50 UTC (rev 1857)
+++ branches/dadwifi-openhal/openhal/ah_devid.h 2006-12-14 19:22:00 UTC (rev 1858)
@@ -35,7 +35,14 @@
#define PCI_PRODUCT_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
#define PCI_PRODUCT_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
#define PCI_PRODUCT_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
+#define PCI_PRODUCT_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
+#define PCI_PRODUCT_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
+#define AR5K_DEVID_AR2413 PCI_PRODUCT_ATHEROS_AR2413
+#define AR5K_DEVID_AR5413 PCI_PRODUCT_ATHEROS_AR5413
+#define AR5K_DEVID_AR5424 PCI_PRODUCT_ATHEROS_AR5424
+
+
/*Combatibility with MadWiFi's definitions (bimary HAL)*/
#define ATHEROS_VENDOR_ID PCI_VENDOR_ATHEROS /* Atheros PCI vendor ID */
@@ -71,6 +78,8 @@
#define AR5212_DEVID_0018 PCI_PRODUCT_ATHEROS_AR5212_0018
#define AR5212_DEVID_0019 PCI_PRODUCT_ATHEROS_AR5212_0019
#define AR5212_AR2413 PCI_PRODUCT_ATHEROS_AR2413 /* AR2413 aka Griffin-lite */
+#define AR5212_AR5413 PCI_PRODUCT_ATHEROS_AR5413 /* Eagle */
+#define AR5212_AR5424 PCI_PRODUCT_ATHEROS_AR5424 /* Condor (PCI express) */
/*Not-supported by OpenHAL*/
/* AR5213 */
Modified: branches/dadwifi-openhal/openhal/ar5210.c
===================================================================
--- branches/dadwifi-openhal/openhal/ar5210.c 2006-12-14 19:00:50 UTC (rev 1857)
+++ branches/dadwifi-openhal/openhal/ar5210.c 2006-12-14 19:22:00 UTC (rev 1858)
@@ -178,14 +178,16 @@
AR5K_HAL_FUNCTION(hal, ar5210, num_tx_pending);
AR5K_HAL_FUNCTION(hal, ar5210, phy_disable);
AR5K_HAL_FUNCTION(hal, ar5210, set_pcu_config);
+ AR5K_HAL_FUNCTION(hal, ar5210, set_txpower_limit);
+ AR5K_HAL_FUNCTION(hal, ar5210, set_def_antenna);
+ AR5K_HAL_FUNCTION(hal, ar5210, get_def_antenna);
/*Totaly unimplemented*/
AR5K_HAL_FUNCTION(hal, ar5210, set_capability);
AR5K_HAL_FUNCTION(hal, ar5210, proc_mib_event);
AR5K_HAL_FUNCTION(hal, ar5210, get_tx_inter_queue);
- AR5K_HAL_FUNCTION(hal, ar5210, set_txpower_limit);
- AR5K_HAL_FUNCTION(hal, ar5210, set_def_antenna);
- AR5K_HAL_FUNCTION(hal, ar5210, get_def_antenna);
+
+
}
struct ath_hal * /*Ported & removed an arg from call to set_associd*/
@@ -461,7 +463,7 @@
ar5k_ar5210_set_def_antenna(struct ath_hal *hal, u_int ant)
{
AR5K_TRACE;
- return;
+ return 0;
}
u_int/*Unimplemented*/
@@ -732,7 +734,7 @@
int
ar5k_ar5210_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
- const HAL_TXQ_INFO *queue_info)
+ HAL_TXQ_INFO *queue_info)
{
u_int queue;
@@ -758,6 +760,7 @@
hal->ah_txq[queue].tqi_type = queue_type;
if (queue_info != NULL) {
+ queue_info->tqi_type = queue_type;
if (ar5k_ar5210_setup_tx_queueprops(hal,
queue, queue_info) != AH_TRUE)
return (-1);
@@ -2127,8 +2130,11 @@
HAL_BOOL /*Unimplemented*/
ar5k_ar5210_set_txpower_limit(struct ath_hal *hal, u_int32_t power)
{
+ HAL_CHANNEL *channel = &hal->ah_current_channel;
+
AR5K_TRACE;
- return (AH_FALSE);
+ AR5K_PRINTF("changing txpower to %d\n unimplemented ;-(",power);
+ return AH_FALSE;
}
/*
Modified: branches/dadwifi-openhal/openhal/ar5211.c
===================================================================
--- branches/dadwifi-openhal/openhal/ar5211.c 2006-12-14 19:00:50 UTC (rev 1857)
+++ branches/dadwifi-openhal/openhal/ar5211.c 2006-12-14 19:22:00 UTC (rev 1858)
@@ -182,14 +182,15 @@
AR5K_HAL_FUNCTION(hal, ar5211, num_tx_pending);
AR5K_HAL_FUNCTION(hal, ar5211, phy_disable);
AR5K_HAL_FUNCTION(hal, ar5211, set_pcu_config);
+ AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit);
+ AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna);
+ AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna);
/*Totaly unimplemented*/
AR5K_HAL_FUNCTION(hal, ar5211, set_capability);
AR5K_HAL_FUNCTION(hal, ar5211, proc_mib_event);
AR5K_HAL_FUNCTION(hal, ar5211, get_tx_inter_queue);
- AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit);
- AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna);
- AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna);
+
}
struct ath_hal * /*Ported & removed an arg from call to set_associd*/
@@ -447,23 +448,29 @@
*/
hal->ah_op_mode = op_mode;
- if (channel->c_channel_flags & IEEE80211_CHAN_A) {
+ switch (channel->c_channel_flags & CHANNEL_MODES) {
+ case CHANNEL_A:
mode = AR5K_INI_VAL_11A;
freq = AR5K_INI_RFGAIN_5GHZ;
ee_mode = AR5K_EEPROM_MODE_11A;
- } else if (channel->c_channel_flags & IEEE80211_CHAN_T) {
+ break ;
+ case CHANNEL_T:
mode = AR5K_INI_VAL_11A_TURBO;
freq = AR5K_INI_RFGAIN_5GHZ;
ee_mode = AR5K_EEPROM_MODE_11A;
- } else if (channel->c_channel_flags & IEEE80211_CHAN_B) {
+ break;
+ case CHANNEL_B:
mode = AR5K_INI_VAL_11B;
freq = AR5K_INI_RFGAIN_2GHZ;
ee_mode = AR5K_EEPROM_MODE_11B;
- } else if (channel->c_channel_flags & IEEE80211_CHAN_G) {
+ break;
+ case CHANNEL_G:
+ case CHANNEL_PUREG:
mode = AR5K_INI_VAL_11G;
freq = AR5K_INI_RFGAIN_2GHZ;
ee_mode = AR5K_EEPROM_MODE_11G;
- } else {
+ break;
+ default:
AR5K_PRINTF("invalid channel: %d\n", channel->c_channel);
return (AH_FALSE);
}
@@ -524,15 +531,10 @@
AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44),
hal->ah_antenna[ee_mode][0], 0xfffffc06);
- ant[0] = HAL_ANT_FIXED_A;
- ant[1] = HAL_ANT_FIXED_B;
-
- if (hal->ah_ant_diversity == AH_FALSE) {
if (freq == AR5K_INI_RFGAIN_2GHZ)
- ant[0] = HAL_ANT_FIXED_B;
- else if (freq == AR5K_INI_RFGAIN_5GHZ)
- ant[1] = HAL_ANT_FIXED_A;
- }
+ ant[0] = ant[1] =HAL_ANT_FIXED_B;
+ else
+ ant[0] = ant[1] = HAL_ANT_FIXED_A;
AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0,
hal->ah_antenna[ee_mode][ant[0]]);
@@ -666,18 +668,21 @@
return (AH_TRUE);
}
-void /*Unimplemented*/
+void /*New*/
ar5k_ar5211_set_def_antenna(struct ath_hal *hal, u_int ant)
{
AR5K_TRACE;
+ /*Just a try M.F.*/
+ AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, ant);
return;
}
-u_int/*Unimplemented*/
+u_int/*New*/
ar5k_ar5211_get_def_antenna(struct ath_hal *hal)
{
AR5K_TRACE;
- return 0;
+ /*Just a try M.F.*/
+ return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA);
}
void
@@ -807,7 +812,7 @@
int
ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
- const HAL_TXQ_INFO *queue_info)
+ HAL_TXQ_INFO *queue_info)
{
u_int queue;
@@ -836,6 +841,7 @@
hal->ah_txq[queue].tqi_type = queue_type;
if (queue_info != NULL) {
+ queue_info->tqi_type = queue_type;
if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info)
!= AH_TRUE)
return (-1);
@@ -852,7 +858,7 @@
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
- if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE)
+ if (hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE)
return (AH_FALSE);
bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
@@ -2224,8 +2230,11 @@
HAL_BOOL /*Unimplemented*/
ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int32_t power)
{
+ HAL_CHANNEL *channel = &hal->ah_current_channel;
+
AR5K_TRACE;
- return (AH_FALSE);
+ AR5K_PRINTF("changing txpower to %d\n unimplemented ;-(",power);
+ return AH_FALSE;
}
/*
@@ -2514,12 +2523,13 @@
if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) {
hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
- hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
if (AR5K_EEPROM_HDR_11B(ee_header))
hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
+#if 0
if (AR5K_EEPROM_HDR_11G(ee_header))
hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
+#endif
}
/* GPIO */
Modified: branches/dadwifi-openhal/openhal/ar5212.c
===================================================================
--- branches/dadwifi-openhal/openhal/ar5212.c 2006-12-14 19:00:50 UTC (rev 1857)
+++ branches/dadwifi-openhal/openhal/ar5212.c 2006-12-14 19:22:00 UTC (rev 1858)
@@ -58,7 +58,7 @@
* Reset functions
*/
AR5K_HAL_FUNCTION(hal, ar5212, reset);
- //AR5K_HAL_FUNCTION(hal, ar5212, set_opmode);
+ AR5K_HAL_FUNCTION(hal, ar5212, set_opmode);
AR5K_HAL_FUNCTION(hal, ar5212, calibrate);
/*
@@ -181,14 +181,15 @@
AR5K_HAL_FUNCTION(hal, ar5212, num_tx_pending);
AR5K_HAL_FUNCTION(hal, ar5212, phy_disable);
AR5K_HAL_FUNCTION(hal, ar5212, set_pcu_config);
+ AR5K_HAL_FUNCTION(hal, ar5212, set_txpower_limit);
+ AR5K_HAL_FUNCTION(hal, ar5212, set_def_antenna);
+ AR5K_HAL_FUNCTION(hal, ar5212, get_def_antenna);
/*Totaly unimplemented*/
AR5K_HAL_FUNCTION(hal, ar5212, set_capability);
AR5K_HAL_FUNCTION(hal, ar5212, proc_mib_event);
AR5K_HAL_FUNCTION(hal, ar5212, get_tx_inter_queue);
- AR5K_HAL_FUNCTION(hal, ar5212, set_txpower_limit);
- AR5K_HAL_FUNCTION(hal, ar5212, set_def_antenna);
- AR5K_HAL_FUNCTION(hal, ar5212, get_def_antenna);
+
}
struct ath_hal * /*Ported & removed an arg from call to set_associd*/
@@ -328,8 +329,8 @@
*/
/* ...reset chipset and PCI device */
- if (ar5k_ar5212_nic_reset(hal,
- AR5K_AR5212_RC_CHIP | AR5K_AR5212_RC_PCI) == AH_FALSE) {
+ if (hal->ah_single_chip == AH_FALSE &&
+ ar5k_ar5212_nic_reset(hal,AR5K_AR5212_RC_CHIP | AR5K_AR5212_RC_PCI) == AH_FALSE) {
AR5K_PRINT("failed to reset the AR5212 + PCI chipset\n");
return (AH_FALSE);
}
@@ -498,31 +499,39 @@
return (AH_FALSE);
}
- if (channel->c_channel_flags & IEEE80211_CHAN_A) {
+ switch (channel->c_channel_flags & CHANNEL_MODES) {
+ case CHANNEL_A:
mode = AR5K_INI_VAL_11A;
freq = AR5K_INI_RFGAIN_5GHZ;
ee_mode = AR5K_EEPROM_MODE_11A;
- } else if (channel->c_channel_flags & IEEE80211_CHAN_T) {
- mode = AR5K_INI_VAL_11A_TURBO;
- freq = AR5K_INI_RFGAIN_5GHZ;
- ee_mode = AR5K_EEPROM_MODE_11A;
- } else if (channel->c_channel_flags & IEEE80211_CHAN_B) {
+ break;
+ case CHANNEL_B:
mode = AR5K_INI_VAL_11B;
freq = AR5K_INI_RFGAIN_2GHZ;
ee_mode = AR5K_EEPROM_MODE_11B;
- } else if (channel->c_channel_flags & IEEE80211_CHAN_G) {
+ break;
+ case CHANNEL_G:
+ case CHANNEL_PUREG:
mode = AR5K_INI_VAL_11G;
freq = AR5K_INI_RFGAIN_2GHZ;
ee_mode = AR5K_EEPROM_MODE_11G;
- } else if (channel->c_channel_flags & CHANNEL_TG) {
+ break;
+ case CHANNEL_T:
+ mode = AR5K_INI_VAL_11A_TURBO;
+ freq = AR5K_INI_RFGAIN_5GHZ;
+ ee_mode = AR5K_EEPROM_MODE_11A;
+ break;
+ case CHANNEL_TG:
mode = AR5K_INI_VAL_11G_TURBO;
freq = AR5K_INI_RFGAIN_2GHZ;
ee_mode = AR5K_EEPROM_MODE_11G;
- } else if (channel->c_channel_flags & CHANNEL_XR) {
+ break;
+ case CHANNEL_XR:
mode = AR5K_INI_VAL_XR;
freq = AR5K_INI_RFGAIN_5GHZ;
ee_mode = AR5K_EEPROM_MODE_11A;
- } else {
+ break;
+ default:
AR5K_PRINTF("invalid channel: %d\n", channel->c_channel);
*status = HAL_EINVAL;
return (AH_FALSE);
@@ -683,16 +692,12 @@
AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x44),
hal->ah_antenna[ee_mode][0], 0xfffffc06);
- ant[0] = HAL_ANT_FIXED_A;
- ant[1] = HAL_ANT_FIXED_B;
-
- if (hal->ah_ant_diversity == AH_FALSE) {
if (freq == AR5K_INI_RFGAIN_2GHZ)
- ant[0] = HAL_ANT_FIXED_B;
+ ant[0] = ant[1] = HAL_ANT_FIXED_B;
else
- ant[1] = HAL_ANT_FIXED_A;
- }
+ ant[0] = ant[1] = HAL_ANT_FIXED_A;
+
AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0,
hal->ah_antenna[ee_mode][ant[0]]);
AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1,
@@ -846,18 +851,21 @@
return (AH_TRUE);
}
-void /*Unimplemented*/
+void /*New*/
ar5k_ar5212_set_def_antenna(struct ath_hal *hal, u_int ant)
{
AR5K_TRACE;
+ /*Just a try M.F.*/
+ AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, ant);
return;
}
-u_int/*Unimplemented*/
+u_int/*New*/
ar5k_ar5212_get_def_antenna(struct ath_hal *hal)
{
AR5K_TRACE;
- return 0;
+ /*Just a try M.F.*/
+ return AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA);
}
void /*O.K.*/
@@ -1000,7 +1008,7 @@
int /*O.K.*/
ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
- const HAL_TXQ_INFO *queue_info)
+ HAL_TXQ_INFO *queue_info)
{
u_int queue;
AR5K_TRACE;
@@ -1030,6 +1038,7 @@
hal->ah_txq[queue].tqi_type = queue_type;
if (queue_info != NULL) {
+ queue_info->tqi_type = queue_type;
if (ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info)
!= AH_TRUE)
return (-1);
@@ -1341,7 +1350,7 @@
return (AH_TRUE);
}
-HAL_BOOL /*O.K. - Initialize tx_desc and clear ds_hw */
+HAL_BOOL /*O.K. - Initialize tx_desc */
ar5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power,
u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode,
@@ -1351,16 +1360,8 @@
AR5K_TRACE;
- /*Got that from roofnet*/
-// if (flags & HAL_TXDESC_NOACK) {
-// tx_tries0 = 1;
-// }
-
tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0;
- /*Clear ds_hw*/
- bzero(desc->ds_hw, sizeof(desc->ds_hw));
-
/*
* Validate input
*/
@@ -1437,12 +1438,14 @@
u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment, const struct ath_desc *last_desc)
{
struct ar5k_ar5212_tx_desc *tx_desc;
+ struct ar5k_ar5212_tx_status *tx_status;
AR5K_TRACE;
tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0;
+ tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2];
- /* Clear status descriptor (we 've clean it during setup)*/
-// bzero(desc->ds_hw, sizeof(desc->ds_hw));
+ /* Clear status descriptor */
+ bzero(tx_status, sizeof(struct ar5k_ar5212_tx_status));
/* Validate segment length and initialize the descriptor */
if ((tx_desc->tx_control_1 = (segment_length &
@@ -2995,12 +2998,13 @@
if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) {
hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
- hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
if (AR5K_EEPROM_HDR_11B(ee_header))
hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
+#if 0
if (AR5K_EEPROM_HDR_11G(ee_header))
hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
+#endif
}
/* GPIO */
@@ -3169,9 +3173,13 @@
return (AH_TRUE);
}
-HAL_BOOL /*Unimplemented*/
-ar5k_ar5212_set_txpower_limit(struct ath_hal *hal, u_int32_t power)
+HAL_BOOL /*New*/
+ar5k_ar5212_set_txpower_limit(struct ath_hal *hal, u_int power)
{
+ /*Just a try M.F.*/
+ HAL_CHANNEL *channel = &hal->ah_current_channel;
+
AR5K_TRACE;
- return (AH_FALSE);
+ AR5K_PRINTF("changing txpower to %d\n",power);
+ return (ar5k_ar5212_txpower(hal, channel, power));
}
Modified: branches/dadwifi-openhal/openhal/ar5xxx.c
===================================================================
--- branches/dadwifi-openhal/openhal/ar5xxx.c 2006-12-14 19:00:50 UTC (rev 1857)
+++ branches/dadwifi-openhal/openhal/ar5xxx.c 2006-12-14 19:22:00 UTC (rev 1858)
@@ -88,7 +88,11 @@
{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0019,
ar5k_ar5212_attach },
{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2413,
- ar5k_ar5212_attach }
+ ar5k_ar5212_attach },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5413,
+ ar5k_ar5212_attach },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5424,
+ ar5k_ar5212_attach },
};
static const HAL_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A;
@@ -227,16 +231,20 @@
hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
switch (device) {
- case PCI_PRODUCT_ATHEROS_AR2413:
- case PCI_PRODUCT_ATHEROS_AR5413:
- case PCI_PRODUCT_ATHEROS_AR5424:
- /* Known single chip solutions */
- hal->ah_single_chip = AH_TRUE;
- break;
- default:
- /* Multi chip solutions */
- hal->ah_single_chip = AH_FALSE;
- break;
+ case PCI_PRODUCT_ATHEROS_AR2413:
+ case PCI_PRODUCT_ATHEROS_AR5413:
+ case PCI_PRODUCT_ATHEROS_AR5424:
+ /*
+ * Known single chip solutions
+ */
+ hal->ah_single_chip = AH_TRUE;
+ break;
+ default:
+ /*
+ * Multi chip solutions
+ */
+ hal->ah_single_chip = AH_FALSE;
+ break;
}
if ((attach)(device, hal, st, sh, status) == NULL)
@@ -437,9 +445,9 @@
IEEE80211_CHAN_2GHZ);
max = ath_hal_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX,
IEEE80211_CHAN_2GHZ);
- flags = CHANNEL_B | CHANNEL_TG |
+ flags = CHANNEL_B /*| CHANNEL_TG |
(hal->ah_version == AR5K_AR5211 ?
- CHANNEL_PUREG : CHANNEL_G);
+ CHANNEL_PUREG : CHANNEL_G)*/;
debugchan:
for (i = min; i <= max && c < max_channels; i++) {
@@ -521,10 +529,12 @@
continue;
/* Match modes */
- if (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK)
+ if ((hal->ah_capabilities.cap_mode & HAL_MODE_11B) &&
+ (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK))
all_channels[c].c_channel_flags = CHANNEL_B;
- if (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM) {
+ if ((hal->ah_capabilities.cap_mode & HAL_MODE_11G) &&
+ (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)) {
all_channels[c].c_channel_flags |=
hal->ah_version == AR5K_AR5211 ?
CHANNEL_PUREG : CHANNEL_G;
@@ -556,6 +566,14 @@
int i;
for (i = 0; i < AR5K_ELEMENTS(names); i++) {
+ if (type == AR5K_VERSION_DEV) {
+ if (names[i].sr_type == type &&
+ names[i].sr_val == val) {
+ name = names[i].sr_name;
+ break;
+ }
+ continue;
+ }
if (names[i].sr_type != type ||
names[i].sr_val == AR5K_SREV_UNKNOWN)
continue;
@@ -1773,11 +1791,11 @@
max = AR5K_EEPROM_PCDAC_STOP;
for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
hal->ah_txpower.txp_pcdac[i] =
-#ifdef notyet
+//#ifdef notyet
min + ((i * (max - min)) / n);
-#else
- min;
-#endif
+//#else
+// min;
+//#endif
}
/* Functions not found in OpenBSD */
Modified: branches/dadwifi-openhal/openhal/ar5xxx.h
===================================================================
--- branches/dadwifi-openhal/openhal/ar5xxx.h 2006-12-14 19:00:50 UTC (rev 1857)
+++ branches/dadwifi-openhal/openhal/ar5xxx.h 2006-12-14 19:22:00 UTC (rev 1858)
@@ -97,16 +97,16 @@
* error occurs--i.e. you cannot check it for success.
*/
typedef enum {
- HAL_OK = 0, /* No error */
- HAL_ENXIO = 1, /* No hardware present */
- HAL_ENOMEM = 2, /* Memory allocation failed */
- HAL_EIO = 3, /* Hardware didn't respond as expected */
- HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
- HAL_EEVERSION = 5, /* EEPROM version invalid */
- HAL_EELOCKED = 6, /* EEPROM unreadable */
- HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
- HAL_EEREAD = 8, /* EEPROM read problem */
- HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
+ HAL_OK = 0, /* No error */
+ HAL_ENXIO = 1, /* No hardware present */
+ HAL_ENOMEM = 2, /* Memory allocation failed */
+ HAL_EIO = 3, /* Hardware didn't respond as expected */
+ HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
+ HAL_EEVERSION = 5, /* EEPROM version invalid */
+ HAL_EELOCKED = 6, /* EEPROM unreadable */
+ HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
+ HAL_EEREAD = 8, /* EEPROM read problem */
+ HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
HAL_EESIZE = 10, /* EEPROM size not supported */
HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
HAL_EINVAL = 12, /* Invalid parameter to function */
@@ -121,17 +121,17 @@
} HAL_BOOL;
enum {
- HAL_MODE_11A = 0x001, /* 11a channels */
- HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
- HAL_MODE_11B = 0x004, /* 11b channels */
- HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
- HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
-// HAL_MODE_11G = 0x008, /* XXX historical */
- HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
- HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
- HAL_MODE_XR = 0x100, /* XR channels */
- HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */
- HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */
+ HAL_MODE_11A = 0x001, /* 11a channels */
+ HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
+ HAL_MODE_11B = 0x004, /* 11b channels */
+ HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
+ HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
+// HAL_MODE_11G = 0x008, /* XXX historical */
+ HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
+ HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
+ HAL_MODE_XR = 0x100, /* XR channels */
+ HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */
+ HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */
HAL_MODE_ALL = 0xfff
};
@@ -164,11 +164,11 @@
#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
typedef enum {
- HAL_TX_QUEUE_ID_DATA_MIN = 0,
- HAL_TX_QUEUE_ID_DATA_MAX = 6,
- HAL_TX_QUEUE_ID_PSPOLL = 7,
- HAL_TX_QUEUE_ID_BEACON = 8,
- HAL_TX_QUEUE_ID_CAB = 9,
+ HAL_TX_QUEUE_ID_DATA_MIN = 0,
+ HAL_TX_QUEUE_ID_DATA_MAX = 6,
+ HAL_TX_QUEUE_ID_PSPOLL = 7,
+ HAL_TX_QUEUE_ID_BEACON = 8,
+ HAL_TX_QUEUE_ID_CAB = 9,
} HAL_TX_QUEUE_ID;
/*
@@ -615,7 +615,10 @@
#define CHANNEL_PUREG (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM)
#define CHANNEL_T (CHANNEL_A | IEEE80211_CHAN_TURBO)
#define CHANNEL_TG (CHANNEL_PUREG | IEEE80211_CHAN_TURBO)
+#define CHANNEL_108G CHANNEL_TG
#define CHANNEL_XR (CHANNEL_A | IEEE80211_CHAN_XR)
+#define CHANNEL_MODES (CHANNEL_A | CHANNEL_B | CHANNEL_G | CHANNEL_PUREG | \
+ CHANNEL_T | CHANNEL_TG | CHANNEL_XR)
typedef enum {
HAL_CHIP_5GHZ = IEEE80211_CHAN_5GHZ,
@@ -1156,7 +1159,7 @@
_t HAL_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, \
HAL_BOOL level); \
_t int (_a _n##_setup_tx_queue)(struct ath_hal *, HAL_TX_QUEUE, \
- const HAL_TXQ_INFO *); \
+ HAL_TXQ_INFO *); \
_t HAL_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \
const HAL_TXQ_INFO *); \
_t HAL_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \
@@ -1215,10 +1218,10 @@
_t void (_a _n##_set_ledstate)(struct ath_hal*, HAL_LED_STATE); \
_t void (_a _n##_set_associd)(struct ath_hal*, \
const u_int8_t *bssid, u_int16_t assocId); \
+ _t HAL_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, \
+ u_int32_t gpio); \
_t HAL_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, \
u_int32_t gpio); \
- _t HAL_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, \
- u_int32_t gpio); \
_t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \
_t HAL_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, \
u_int32_t val); \
@@ -1230,8 +1233,6 @@
_t HAL_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \
_t void (_a _n##_update_mib_counters)(struct ath_hal*, \
HAL_MIB_STATS*); \
- _t HAL_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, \
- HAL_CIPHER); \
_t HAL_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \
_t HAL_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \
_t u_int (_a _n##_get_slot_time)(struct ath_hal*); \
@@ -1240,6 +1241,8 @@
_t HAL_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \
_t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \
/* Key Cache Functions */ \
+ _t HAL_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, \
+ HAL_CIPHER); \
_t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \
_t HAL_BOOL (_a _n##_reset_key)(struct ath_hal*, \
u_int16_t); \
@@ -1287,14 +1290,15 @@
_t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \
_t HAL_BOOL (_a _n##_phy_disable)(struct ath_hal *);\
_t void (_a _n##_set_pcu_config)(struct ath_hal *);\
+ _t HAL_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \
+ _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int);\
+ _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *);\
/*Totaly unimplemented*/ \
_t HAL_BOOL (_a _n##_set_capability)(struct ath_hal *, HAL_CAPABILITY_TYPE, u_int32_t, u_int32_t, HAL_STATUS *) ; \
_t void (_a _n##_proc_mib_event)(struct ath_hal *, const HAL_NODE_STATS *) ; \
- _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u_int32_t *); \
- _t HAL_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int32_t); \
- _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int);\
- _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *);
+ _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u_int32_t *);
+
#define AR5K_MAX_GPIO 10
#define AR5K_MAX_RF_BANKS 8
@@ -1317,6 +1321,7 @@
HAL_BOOL ah_turbo;
HAL_BOOL ah_calibration;
HAL_BOOL ah_running;
+ HAL_BOOL ah_single_chip;
HAL_RFGAIN ah_rf_gain;
HAL_RATE_TABLE ah_rt_11a;
@@ -1340,7 +1345,7 @@
HAL_BOOL ah_2ghz;
#define ah_regdomain ah_capabilities.cap_regdomain.reg_current
-#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
+#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
#define ah_modes ah_capabilities.cap_mode
#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
#define ah_countryCode ah_country_code
@@ -1403,7 +1408,8 @@
enum ar5k_srev_type {
AR5K_VERSION_VER,
AR5K_VERSION_REV,
- AR5K_VERSION_RAD
+ AR5K_VERSION_RAD,
+ AR5K_VERSION_DEV
};
struct ar5k_srev_name {
@@ -1425,10 +1431,14 @@
{ "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \
{ "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \
{ "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \
- { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \
+ { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \
{ "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \
{ "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \
- { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN } \
+ { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \
+ { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \
+ { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \
+ { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \
+ { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \
}
#define AR5K_SREV_UNKNOWN 0xffff
@@ -1508,7 +1518,7 @@
*/
#define AR5K_INIT_MODE ( \
- IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN \
+ IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK \
)
#define AR5K_INIT_TX_LATENCY 502
#define AR5K_INIT_USEC 39
@@ -2153,7 +2163,7 @@
HAL_BOOL ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *,
u_int, u_int *, HAL_CTRY_CODE, u_int16_t, HAL_BOOL, HAL_BOOL);
-const char *ar5k_printver(enum ar5k_srev_type, u_int);
+const char *ar5k_printver(enum ar5k_srev_type, u_int32_t);
void ar5k_radar_alert(struct ath_hal *);
ieee80211_regdomain_t ar5k_regdomain_to_ieee(u_int16_t);
u_int16_t ar5k_regdomain_from_ieee(ieee80211_regdomain_t);
|