[Madwifi-cvs] revision 1441 committed by mrenzmann
Status: Beta
Brought to you by:
otaku
From: mrenzmann <svn...@ma...> - 2006-02-06 16:03:46
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Project : madwifi Revision : 1441 Author : mrenzmann Date : 2006-02-06 17:03:21 +0100 (Mon, 06 Feb 2006) Log Message : Some more code cleanup (again just regarding formatting, no functional changes). Signed-off-by: Michael Renzmann <mre...@ot...> Affected Files: * trunk/ath/if_ath_ahb.h updated * trunk/ath/if_ath_pci.h updated * trunk/ath/if_athioctl.h updated * trunk/ath/if_athrate.h updated * trunk/ath/if_athvar.h updated * trunk/ath_rate/amrr/amrr.h updated * trunk/ath_rate/onoe/onoe.h updated * trunk/ath_rate/sample/sample.c updated * trunk/ath_rate/sample/sample.h updated * trunk/hal/ah.h updated * trunk/hal/ah_desc.h updated * trunk/hal/linux/ah_osdep.h updated * trunk/include/sys/queue.h updated * trunk/net80211/_ieee80211.h updated * trunk/net80211/ieee80211.h updated * trunk/net80211/ieee80211_crypto.h updated * trunk/net80211/ieee80211_ioctl.h updated * trunk/net80211/ieee80211_linux.h updated * trunk/net80211/ieee80211_monitor.h updated * trunk/net80211/ieee80211_node.h updated * trunk/net80211/ieee80211_power.h updated * trunk/net80211/ieee80211_proto.h updated * trunk/net80211/ieee80211_radiotap.h updated * trunk/net80211/ieee80211_scan.h updated * trunk/net80211/ieee80211_var.h updated * trunk/net80211/if_athproto.h updated * trunk/net80211/if_ethersubr.h updated * trunk/net80211/if_llc.h updated * trunk/net80211/if_media.h updated Modified: trunk/ath/if_ath_ahb.h =================================================================== --- trunk/ath/if_ath_ahb.h 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath/if_ath_ahb.h 2006-02-06 16:03:21 UTC (rev 1441) @@ -14,7 +14,7 @@ #define AR531X_WLAN1_NUM 1 #define REG_WRITE(_reg,_val) *((volatile u_int32_t *)(_reg)) = (_val); -#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) /* * 5315 specific registers @@ -23,78 +23,77 @@ /* * PCI-MAC Configuration registers */ -#define AR5315_PCI 0xB0100000 /* PCI MMR */ -#define AR5315_PCI_MAC_RC (AR5315_PCI + 0x4000) -#define AR5315_PCI_MAC_SCR (AR5315_PCI + 0x4004) -#define AR5315_PCI_MAC_INTPEND (AR5315_PCI + 0x4008) -#define AR5315_PCI_MAC_SFR (AR5315_PCI + 0x400C) -#define AR5315_PCI_MAC_PCICFG (AR5315_PCI + 0x4010) -#define AR5315_PCI_MAC_SREV (AR5315_PCI + 0x4020) +#define AR5315_PCI 0xB0100000 /* PCI MMR */ +#define AR5315_PCI_MAC_RC (AR5315_PCI + 0x4000) +#define AR5315_PCI_MAC_SCR (AR5315_PCI + 0x4004) +#define AR5315_PCI_MAC_INTPEND (AR5315_PCI + 0x4008) +#define AR5315_PCI_MAC_SFR (AR5315_PCI + 0x400C) +#define AR5315_PCI_MAC_PCICFG (AR5315_PCI + 0x4010) +#define AR5315_PCI_MAC_SREV (AR5315_PCI + 0x4020) -#define AR5315_PCI_MAC_RC_MAC 0x00000001 -#define AR5315_PCI_MAC_RC_BB 0x00000002 +#define AR5315_PCI_MAC_RC_MAC 0x00000001 +#define AR5315_PCI_MAC_RC_BB 0x00000002 -#define AR5315_PCI_MAC_SCR_SLMODE_M 0x00030000 -#define AR5315_PCI_MAC_SCR_SLMODE_S 16 -#define AR5315_PCI_MAC_SCR_SLM_FWAKE 0 -#define AR5315_PCI_MAC_SCR_SLM_FSLEEP 1 -#define AR5315_PCI_MAC_SCR_SLM_NORMAL 2 +#define AR5315_PCI_MAC_SCR_SLMODE_M 0x00030000 +#define AR5315_PCI_MAC_SCR_SLMODE_S 16 +#define AR5315_PCI_MAC_SCR_SLM_FWAKE 0 +#define AR5315_PCI_MAC_SCR_SLM_FSLEEP 1 +#define AR5315_PCI_MAC_SCR_SLM_NORMAL 2 -#define AR5315_PCI_MAC_SFR_SLEEP 0x00000001 +#define AR5315_PCI_MAC_SFR_SLEEP 0x00000001 -#define AR5315_PCI_MAC_PCICFG_SPWR_DN 0x00010000 +#define AR5315_PCI_MAC_PCICFG_SPWR_DN 0x00010000 -#define AR5315_IRQ_WLAN0_INTRS 3 -#define AR5315_WLAN0 0xb0000000 +#define AR5315_IRQ_WLAN0_INTRS 3 +#define AR5315_WLAN0 0xb0000000 -#define AR5315_ENDIAN_CTL 0xb100000c -#define AR5315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ -#define AR5315_AHB_ARB_CTL 0xb1000008 -#define AR5315_ARB_WLAN 0x00000002 +#define AR5315_ENDIAN_CTL 0xb100000c +#define AR5315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ +#define AR5315_AHB_ARB_CTL 0xb1000008 +#define AR5315_ARB_WLAN 0x00000002 /* * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). */ -#define AR5315_SREV 0xb1000014 +#define AR5315_SREV 0xb1000014 -#define AR5315_REV_MAJ 0x0080 -#define AR5315_REV_MAJ_M 0x00f0 -#define AR5315_REV_MAJ_S 4 -#define AR5315_REV_MIN_M 0x000f -#define AR5315_REV_MIN_S 0 -#define AR5315_REV_CHIP (REV_MAJ|REV_MIN) +#define AR5315_REV_MAJ 0x0080 +#define AR5315_REV_MAJ_M 0x00f0 +#define AR5315_REV_MAJ_S 4 +#define AR5315_REV_MIN_M 0x000f +#define AR5315_REV_MIN_S 0 +#define AR5315_REV_CHIP (REV_MAJ|REV_MIN) -#define AR531X_IRQ_WLAN0_INTRS 2 -#define AR531X_IRQ_WLAN1_INTRS 5 -#define AR531X_WLAN0 0xb8000000 -#define AR531X_WLAN1 0xb8500000 -#define AR531X_WLANX_LEN 0x000ffffc +#define AR531X_IRQ_WLAN0_INTRS 2 +#define AR531X_IRQ_WLAN1_INTRS 5 +#define AR531X_WLAN0 0xb8000000 +#define AR531X_WLAN1 0xb8500000 +#define AR531X_WLANX_LEN 0x000ffffc -#define AR531X_ENABLE 0xbc003080 -#define AR531X_ENABLE_WLAN1 0x8 -#define AR531X_ENABLE_WLAN0 0x1 -#define AR531X_RADIO_MASK_OFF 0xc8 -#define AR531X_RADIO0_MASK 0x0003 -#define AR531X_RADIO1_MASK 0x000c -#define AR531X_RADIO1_S 2 +#define AR531X_ENABLE 0xbc003080 +#define AR531X_ENABLE_WLAN1 0x8 +#define AR531X_ENABLE_WLAN0 0x1 +#define AR531X_RADIO_MASK_OFF 0xc8 +#define AR531X_RADIO0_MASK 0x0003 +#define AR531X_RADIO1_MASK 0x000c +#define AR531X_RADIO1_S 2 -#define BUS_DMA_FROMDEVICE 0 -#define BUS_DMA_TODEVICE 1 +#define BUS_DMA_FROMDEVICE 0 +#define BUS_DMA_TODEVICE 1 -#define AR531X_APBBASE 0xbc000000 -#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) -#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ -#define AR531X_REV_MAJ 0x00f0 -#define AR531X_REV_MAJ_S 4 -#define AR531X_REV_MIN 0x000f -#define AR531X_REV_MIN_S 0 +#define AR531X_APBBASE 0xbc000000 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ +#define AR531X_REV_MAJ 0x00f0 +#define AR531X_REV_MAJ_S 4 +#define AR531X_REV_MIN 0x000f +#define AR531X_REV_MIN_S 0 #define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ /* set bus cachesize in 4B word units */ -static __inline void bus_dma_sync_single(void *hwdev, - dma_addr_t dma_handle, - size_t size, int direction) +static __inline void bus_dma_sync_single(void *hwdev, dma_addr_t dma_handle, + size_t size, int direction) { unsigned long addr; @@ -103,7 +102,7 @@ } static __inline dma_addr_t bus_map_single(void *hwdev, void *ptr, - size_t size, int direction) + size_t size, int direction) { unsigned long addr = (unsigned long) ptr; @@ -113,7 +112,7 @@ } static __inline void bus_unmap_single(void *hwdev, dma_addr_t dma_addr, - size_t size, int direction) + size_t size, int direction) { if (direction != BUS_DMA_TODEVICE) { unsigned long addr; @@ -122,10 +121,8 @@ dma_cache_wback_inv(addr, size); } } -void *bus_alloc_consistent(void *hwdev, size_t size, - dma_addr_t * dma_handle); -void bus_free_consistent(void *hwdev, size_t size, - void *vaddr, dma_addr_t dma_handle); +void *bus_alloc_consistent(void *, size_t, dma_addr_t *); +void bus_free_consistent(void *, size_t, void *, dma_addr_t); extern const char * get_system_type(void); #define sysRegRead(phys) (*(volatile u_int32_t *)phys) Modified: trunk/ath/if_ath_pci.h =================================================================== --- trunk/ath/if_ath_pci.h 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath/if_ath_pci.h 2006-02-06 16:03:21 UTC (rev 1441) @@ -64,11 +64,11 @@ #endif #ifndef PCI_D0 -#define PCI_D0 0 +#define PCI_D0 0 #endif #ifndef PCI_D3hot -#define PCI_D3hot 3 +#define PCI_D3hot 3 #endif #endif /* _DEV_ATH_PCI_H_ */ Modified: trunk/ath/if_athioctl.h =================================================================== --- trunk/ath/if_athioctl.h 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath/if_athioctl.h 2006-02-06 16:03:21 UTC (rev 1441) @@ -43,61 +43,61 @@ #define _DEV_ATH_ATHIOCTL_H struct ath_stats { - u_int32_t ast_watchdog; /* device reset by watchdog */ - u_int32_t ast_hardware; /* fatal hardware error interrupts */ - u_int32_t ast_bmiss; /* beacon miss interrupts */ - u_int32_t ast_rxorn; /* rx overrun interrupts */ - u_int32_t ast_rxeol; /* rx eol interrupts */ - u_int32_t ast_txurn; /* tx underrun interrupts */ - u_int32_t ast_mib; /* mib interrupts */ - u_int32_t ast_tx_packets; /* packet sent on the interface */ - u_int32_t ast_tx_mgmt; /* management frames transmitted */ - u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ - u_int32_t ast_tx_invalid; /* frames discarded due to is device gone */ - u_int32_t ast_tx_qstop; /* tx queue stopped because it's full */ - u_int32_t ast_tx_encap; /* tx encapsulation failed */ - u_int32_t ast_tx_nonode; /* tx failed due to of no node */ - u_int32_t ast_tx_nobuf; /* tx failed due to of no tx buffer (data) */ - u_int32_t ast_tx_nobufmgt;/* tx failed due to of no tx buffer (mgmt)*/ - u_int32_t ast_tx_xretries;/* tx failed due to of too many retries */ - u_int32_t ast_tx_fifoerr; /* tx failed due to of FIFO underrun */ - u_int32_t ast_tx_filtered;/* tx failed due to xmit filtered */ - u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ - u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ - u_int32_t ast_tx_badrate; /* tx failed due to of bogus xmit rate */ - u_int32_t ast_tx_noack; /* tx frames with no ack marked */ - u_int32_t ast_tx_rts; /* tx frames with rts enabled */ - u_int32_t ast_tx_cts; /* tx frames with cts enabled */ - u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ - u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ - u_int32_t ast_tx_protect; /* tx frames with protection */ - u_int32_t ast_rx_orn; /* rx failed due to of desc overrun */ - u_int32_t ast_rx_crcerr; /* rx failed due to of bad CRC */ - u_int32_t ast_rx_fifoerr; /* rx failed due to of FIFO overrun */ - u_int32_t ast_rx_badcrypt;/* rx failed due to of decryption */ - u_int32_t ast_rx_badmic; /* rx failed due to of MIC failure */ - u_int32_t ast_rx_phyerr; /* rx PHY error summary count */ - u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ - u_int32_t ast_rx_tooshort;/* rx discarded due to frame too short */ - u_int32_t ast_rx_toobig; /* rx discarded due to frame too large */ - u_int32_t ast_rx_nobuf; /* rx setup failed due to of no skbuff */ - u_int32_t ast_rx_packets; /* packet recv on the interface */ - u_int32_t ast_rx_mgt; /* management frames received */ - u_int32_t ast_rx_ctl; /* control frames received */ - int8_t ast_tx_rssi; /* tx rssi of last ack */ - int8_t ast_rx_rssi; /* rx rssi from histogram */ - u_int32_t ast_be_xmit; /* beacons transmitted */ - u_int32_t ast_be_nobuf; /* no skbuff available for beacon */ - u_int32_t ast_per_cal; /* periodic calibration calls */ - u_int32_t ast_per_calfail;/* periodic calibration failed */ - u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ - u_int32_t ast_rate_calls; /* rate control checks */ - u_int32_t ast_rate_raise; /* rate control raised xmit rate */ - u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ - u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ - u_int32_t ast_ant_txswitch;/* tx antenna switches */ - u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ - u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ + u_int32_t ast_watchdog; /* device reset by watchdog */ + u_int32_t ast_hardware; /* fatal hardware error interrupts */ + u_int32_t ast_bmiss; /* beacon miss interrupts */ + u_int32_t ast_rxorn; /* rx overrun interrupts */ + u_int32_t ast_rxeol; /* rx eol interrupts */ + u_int32_t ast_txurn; /* tx underrun interrupts */ + u_int32_t ast_mib; /* mib interrupts */ + u_int32_t ast_tx_packets; /* packet sent on the interface */ + u_int32_t ast_tx_mgmt; /* management frames transmitted */ + u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ + u_int32_t ast_tx_invalid; /* frames discarded due to is device gone */ + u_int32_t ast_tx_qstop; /* tx queue stopped because it's full */ + u_int32_t ast_tx_encap; /* tx encapsulation failed */ + u_int32_t ast_tx_nonode; /* tx failed due to of no node */ + u_int32_t ast_tx_nobuf; /* tx failed due to of no tx buffer (data) */ + u_int32_t ast_tx_nobufmgt; /* tx failed due to of no tx buffer (mgmt)*/ + u_int32_t ast_tx_xretries; /* tx failed due to of too many retries */ + u_int32_t ast_tx_fifoerr; /* tx failed due to of FIFO underrun */ + u_int32_t ast_tx_filtered; /* tx failed due to xmit filtered */ + u_int32_t ast_tx_shortretry; /* tx on-chip retries (short) */ + u_int32_t ast_tx_longretry; /* tx on-chip retries (long) */ + u_int32_t ast_tx_badrate; /* tx failed due to of bogus xmit rate */ + u_int32_t ast_tx_noack; /* tx frames with no ack marked */ + u_int32_t ast_tx_rts; /* tx frames with rts enabled */ + u_int32_t ast_tx_cts; /* tx frames with cts enabled */ + u_int32_t ast_tx_shortpre; /* tx frames with short preamble */ + u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ + u_int32_t ast_tx_protect; /* tx frames with protection */ + u_int32_t ast_rx_orn; /* rx failed due to of desc overrun */ + u_int32_t ast_rx_crcerr; /* rx failed due to of bad CRC */ + u_int32_t ast_rx_fifoerr; /* rx failed due to of FIFO overrun */ + u_int32_t ast_rx_badcrypt; /* rx failed due to of decryption */ + u_int32_t ast_rx_badmic; /* rx failed due to of MIC failure */ + u_int32_t ast_rx_phyerr; /* rx PHY error summary count */ + u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ + u_int32_t ast_rx_tooshort; /* rx discarded due to frame too short */ + u_int32_t ast_rx_toobig; /* rx discarded due to frame too large */ + u_int32_t ast_rx_nobuf; /* rx setup failed due to of no skbuff */ + u_int32_t ast_rx_packets; /* packet recv on the interface */ + u_int32_t ast_rx_mgt; /* management frames received */ + u_int32_t ast_rx_ctl; /* control frames received */ + int8_t ast_tx_rssi; /* tx rssi of last ack */ + int8_t ast_rx_rssi; /* rx rssi from histogram */ + u_int32_t ast_be_xmit; /* beacons transmitted */ + u_int32_t ast_be_nobuf; /* no skbuff available for beacon */ + u_int32_t ast_per_cal; /* periodic calibration calls */ + u_int32_t ast_per_calfail; /* periodic calibration failed */ + u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ + u_int32_t ast_rate_calls; /* rate control checks */ + u_int32_t ast_rate_raise; /* rate control raised xmit rate */ + u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ + u_int32_t ast_ant_defswitch; /* rx/default antenna switches */ + u_int32_t ast_ant_txswitch; /* tx antenna switches */ + u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ + u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ }; struct ath_diag { @@ -117,11 +117,11 @@ #define ATH_RADAR_MUTE_TIME 1 /* Set dfs mute time for dfs test mode */ #ifdef __linux__ -#define SIOCGATHSTATS (SIOCDEVPRIVATE+0) -#define SIOCGATHDIAG (SIOCDEVPRIVATE+1) -#define SIOCGATHRADARSIG (SIOCDEVPRIVATE+2) +#define SIOCGATHSTATS (SIOCDEVPRIVATE+0) +#define SIOCGATHDIAG (SIOCDEVPRIVATE+1) +#define SIOCGATHRADARSIG (SIOCDEVPRIVATE+2) #else -#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) -#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) +#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) +#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) #endif #endif /* _DEV_ATH_ATHIOCTL_H */ Modified: trunk/ath/if_athrate.h =================================================================== --- trunk/ath/if_athrate.h 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath/if_athrate.h 2006-02-06 16:03:21 UTC (rev 1441) @@ -77,14 +77,14 @@ struct ieee80211vap; struct ath_ratectrl { - size_t arc_space; /* space required for per-node state */ - size_t arc_vap_space; /* space required for per-vap state */ + size_t arc_space; /* space required for per-node state */ + size_t arc_vap_space; /* space required for per-vap state */ }; /* * Attach/detach a rate control module. */ struct ath_ratectrl *ath_rate_attach(struct ath_softc *); -void ath_rate_detach(struct ath_ratectrl *); +void ath_rate_detach(struct ath_ratectrl *); /* @@ -94,24 +94,23 @@ * Initialize per-node state already allocated for the specified * node; this space can be assumed initialized to zero. */ -void ath_rate_node_init(struct ath_softc *, struct ath_node *); +void ath_rate_node_init(struct ath_softc *, struct ath_node *); /* * Cleanup any per-node state prior to the node being reclaimed. */ -void ath_rate_node_cleanup(struct ath_softc *, struct ath_node *); +void ath_rate_node_cleanup(struct ath_softc *, struct ath_node *); /* * Update rate control state on station associate/reassociate * (when operating as an ap or for nodes discovered when operating * in ibss mode). */ -void ath_rate_newassoc(struct ath_softc *, struct ath_node *, - int isNewAssociation); +void ath_rate_newassoc(struct ath_softc *, struct ath_node *, int); /* * Update/reset rate control state for 802.11 state transitions. * Important mostly as the analog to ath_rate_newassoc when operating * in station mode. */ -void ath_rate_newstate(struct ieee80211vap *, enum ieee80211_state); +void ath_rate_newstate(struct ieee80211vap *, enum ieee80211_state); /* * Transmit handling. @@ -122,21 +121,20 @@ * and ath_rate_setupxtxdesc will be called after deciding if the frame * can be transmitted with multi-rate retry. */ -void ath_rate_findrate(struct ath_softc *, struct ath_node *, - int shortPreamble, size_t frameLen, - u_int8_t *rix, int *try0, u_int8_t *txrate); +void ath_rate_findrate(struct ath_softc *, struct ath_node *, int, size_t, + u_int8_t *, int *, u_int8_t *); /* * Setup any extended (multi-rate) descriptor state for a data packet. * The rate index returned by ath_rate_findrate is passed back in. */ -void ath_rate_setupxtxdesc(struct ath_softc *, struct ath_node *, - struct ath_desc *, int shortPreamble, u_int8_t rix); +void ath_rate_setupxtxdesc(struct ath_softc *, struct ath_node *, + struct ath_desc *, int, u_int8_t); /* * Update rate control state for a packet associated with the * supplied transmit descriptor. The routine is invoked both * for packets that were successfully sent and for those that * failed (consult the descriptor for details). */ -void ath_rate_tx_complete(struct ath_softc *, struct ath_node *, - const struct ath_desc *); +void ath_rate_tx_complete(struct ath_softc *, struct ath_node *, + const struct ath_desc *); #endif /* _ATH_RATECTRL_H_ */ Modified: trunk/ath/if_athvar.h =================================================================== --- trunk/ath/if_athvar.h 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath/if_athvar.h 2006-02-06 16:03:21 UTC (rev 1441) @@ -73,9 +73,11 @@ #include <linux/tqueue.h> #define ATH_WORK_THREAD tq_struct #define ATH_SCHEDULE_TASK(t) schedule_task((t)) -#define ATH_INIT_SCHED_TASK(t, f, d) do { memset((t),0,sizeof(struct tq_struct)); \ - (t)->routine = (void (*)(void*)) (f); \ - (t)->data=(void *) (d); } while (0) +#define ATH_INIT_SCHED_TASK(t, f, d) do { \ + memset((t),0,sizeof(struct tq_struct)); \ + (t)->routine = (void (*)(void*)) (f); \ + (t)->data=(void *) (d); \ +} while (0) #define ATH_FLUSH_TASKS flush_scheduled_tasks #else #include <linux/workqueue.h> @@ -132,13 +134,13 @@ proc_dointvec(ctl, write, filp, buffer, lenp, ppos) #endif -#define ATH_TIMEOUT 1000 +#define ATH_TIMEOUT 1000 -#define ATH_DFS_WAIT_POLL_PERIOD 2 /* 2 seconds */ -#define ATH_DFS_TEST_RETURN_PERIOD 15 /* 15 seconds */ +#define ATH_DFS_WAIT_POLL_PERIOD 2 /* 2 seconds */ +#define ATH_DFS_TEST_RETURN_PERIOD 15 /* 15 seconds */ -#define ATH_LONG_CALINTERVAL 30 /* 30 seconds between calibrations */ -#define ATH_SHORT_CALINTERVAL 1 /* 1 second between calibrations */ +#define ATH_LONG_CALINTERVAL 30 /* 30 seconds between calibrations */ +#define ATH_SHORT_CALINTERVAL 1 /* 1 second between calibrations */ /* * Maximum acceptable MTU @@ -154,18 +156,17 @@ #define ATH_BCBUF 4 /* number of beacon buffers */ /* free buffer threshold to restart net dev */ -#define ATH_TXBUF_FREE_THRESHOLD (ATH_TXBUF/20) +#define ATH_TXBUF_FREE_THRESHOLD (ATH_TXBUF / 20) #define TAIL_DROP_COUNT 50 /* maximum number of queued frames allowed */ /* * dynamic turbo specific macros. */ +#define ATH_TURBO_UP_THRESH 750000 /* bytes/sec */ +#define ATH_TURBO_DN_THRESH 1000000 /* bytes/sec */ +#define ATH_TURBO_PERIOD_HOLD 1 /* in seconds */ -#define ATH_TURBO_UP_THRESH 750000 /* bytes/sec */ -#define ATH_TURBO_DN_THRESH 1000000 /* bytes/sec */ -#define ATH_TURBO_PERIOD_HOLD 1 /*in seconds */ - /* * The only case where we see skbuff chains is due to FF aggregation in * the driver. @@ -196,45 +197,45 @@ /* XR specific macros */ -#define XR_DEFAULT_GRPPOLL_RATE_STR "0.25 1 1 3 3 6 6 20" -#define GRPPOLL_RATE_STR_LEN 64 -#define XR_SLOT_DELAY 30 // in usec -#define XR_AIFS 0 -#define XR_NUM_RATES 5 -#define XR_NUM_SUP_RATES 8 +#define XR_DEFAULT_GRPPOLL_RATE_STR "0.25 1 1 3 3 6 6 20" +#define GRPPOLL_RATE_STR_LEN 64 +#define XR_SLOT_DELAY 30 /* in usec */ +#define XR_AIFS 0 +#define XR_NUM_RATES 5 +#define XR_NUM_SUP_RATES 8 /* XR uplink should have same cwmin/cwmax value */ -#define XR_CWMIN_CWMAX 7 +#define XR_CWMIN_CWMAX 7 -#define XR_DATA_AIFS 3 -#define XR_DATA_CWMIN 31 -#define XR_DATA_CWMAX 1023 +#define XR_DATA_AIFS 3 +#define XR_DATA_CWMIN 31 +#define XR_DATA_CWMAX 1023 /* pick the threshold so that we meet most of the regulatory constraints */ -#define XR_FRAGMENTATION_THRESHOLD 540 -#define XR_TELEC_FRAGMENTATION_THRESHOLD 442 +#define XR_FRAGMENTATION_THRESHOLD 540 +#define XR_TELEC_FRAGMENTATION_THRESHOLD 442 -#define XR_MAX_GRP_POLL_PERIOD 1000 /* Maximum Group Poll Periodicity */ +#define XR_MAX_GRP_POLL_PERIOD 1000 /* Maximum Group Poll Periodicity */ -#define XR_DEFAULT_POLL_INTERVAL 100 -#define XR_MIN_POLL_INTERVAL 30 -#define XR_MAX_POLL_INTERVAL 1000 -#define XR_DEFAULT_POLL_COUNT 32 -#define XR_MIN_POLL_COUNT 16 -#define XR_MAX_POLL_COUNT 64 -#define XR_POLL_UPDATE_PERIOD 10 /* number of xr beacons */ -#define XR_GRPPOLL_PERIOD_FACTOR 5 /* factor used in calculating grp poll interval */ -#define XR_4MS_FRAG_THRESHOLD 128 /* fragmentation threshold for 4msec frame limit */ +#define XR_DEFAULT_POLL_INTERVAL 100 +#define XR_MIN_POLL_INTERVAL 30 +#define XR_MAX_POLL_INTERVAL 1000 +#define XR_DEFAULT_POLL_COUNT 32 +#define XR_MIN_POLL_COUNT 16 +#define XR_MAX_POLL_COUNT 64 +#define XR_POLL_UPDATE_PERIOD 10 /* number of XR beacons */ +#define XR_GRPPOLL_PERIOD_FACTOR 5 /* factor used in calculating grp poll interval */ +#define XR_4MS_FRAG_THRESHOLD 128 /* fragmentation threshold for 4msec frame limit */ /* * Maximum Values in ms for group poll periodicty */ -#define GRP_POLL_PERIOD_NO_XR_STA_MAX 100 -#define GRP_POLL_PERIOD_XR_STA_MAX 30 +#define GRP_POLL_PERIOD_NO_XR_STA_MAX 100 +#define GRP_POLL_PERIOD_XR_STA_MAX 30 /* * Percentage of the configured poll periodicity */ -#define GRP_POLL_PERIOD_FACTOR_XR_STA 30 /* When XR Stations associated freq is 30% higher */ +#define GRP_POLL_PERIOD_FACTOR_XR_STA 30 /* When XR Stations associated freq is 30% higher */ #define A_MAX(a,b) ((a) > (b) ? (a) : (b)) @@ -247,13 +248,13 @@ */ #define GRP_POLL_PERIOD_NO_XR_STA(sc) (sc->sc_xrpollint) #define GRP_POLL_PERIOD_XR_STA(sc) \ - A_MAX(GRP_POLL_PERIOD_FACTOR_XR_STA * (sc->sc_xrpollint / 100),GRP_POLL_PERIOD_XR_STA_MAX) + A_MAX(GRP_POLL_PERIOD_FACTOR_XR_STA * (sc->sc_xrpollint / 100), GRP_POLL_PERIOD_XR_STA_MAX) /* * When there are no XR STAs and a valid double chirp is received then the Group Polls are * transmitted for 10 seconds from the time of the last valid double double-chirp */ -#define NO_XR_STA_GRPPOLL_TX_DUR 10000 +#define NO_XR_STA_GRPPOLL_TX_DUR 10000 /* @@ -265,30 +266,31 @@ * up to ATH_KEYMAX entries (could dynamically allocate state). */ #define ATH_KEYMAX 128 /* max key cache size we handle */ -#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ +#define ATH_KEYBYTES (ATH_KEYMAX / NBBY) /* storage space in bytes */ #define ATH_MIN_FF_RATE 12000 /* min rate fof ff aggragattion.in Kbps */ #define ATH_MIN_FF_RATE 12000 /* min rate fof ff aggragattion.in Kbps */ struct ath_buf; typedef STAILQ_HEAD(, ath_buf) ath_bufhead; + /* driver-specific node state */ struct ath_node { - struct ieee80211_node an_node; /* base class */ - u_int16_t an_decomp_index; /* decompression mask index */ - u_int32_t an_avgrssi; /* average rssi over all rx frames */ - u_int8_t an_prevdatarix; /* rate ix of last data frame */ - u_int16_t an_minffrate; /* mimum rate in kbps for ff to aggragate */ - HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */ - struct ath_buf *an_tx_ffbuf[WME_NUM_AC]; /* ff staging area */ - ath_bufhead an_uapsd_q; /* U-APSD delivery queue */ - int an_uapsd_qdepth; /* U-APSD delivery queue depth */ - ath_bufhead an_uapsd_overflowq; /* U-APSD overflow queue (for > MaxSp frames) */ - int an_uapsd_overflowqdepth; /* U-APSD overflow queue depth */ - spinlock_t an_uapsd_lock; /* U-APSD deleivery queue lock */ - unsigned long an_uapsd_lockflags; /* U-APSD cli flags for lock */ + struct ieee80211_node an_node; /* base class */ + u_int16_t an_decomp_index; /* decompression mask index */ + u_int32_t an_avgrssi; /* average rssi over all rx frames */ + u_int8_t an_prevdatarix; /* rate ix of last data frame */ + u_int16_t an_minffrate; /* mimum rate in kbps for ff to aggragate */ + HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */ + struct ath_buf *an_tx_ffbuf[WME_NUM_AC]; /* ff staging area */ + ath_bufhead an_uapsd_q; /* U-APSD delivery queue */ + int an_uapsd_qdepth; /* U-APSD delivery queue depth */ + ath_bufhead an_uapsd_overflowq; /* U-APSD overflow queue (for > MaxSp frames) */ + int an_uapsd_overflowqdepth; /* U-APSD overflow queue depth */ + spinlock_t an_uapsd_lock; /* U-APSD deleivery queue lock */ + unsigned long an_uapsd_lockflags; /* U-APSD cli flags for lock */ /* variable-length rate control state follows */ }; -#define ATH_NODE(_n) ((struct ath_node *)(_n)) -#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) +#define ATH_NODE(_n) ((struct ath_node *)(_n)) +#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) #define ATH_NODE_UAPSD_LOCK_INIT(_an) spin_lock_init(&(_an)->an_uapsd_lock) #define ATH_NODE_UAPSD_LOCK(_an) spin_lock(&(_an)->an_uapsd_lock) #define ATH_NODE_UAPSD_UNLOCK(_an) spin_unlock(&(_an)->an_uapsd_lock) @@ -306,30 +308,31 @@ x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ } while (0) -#define ATH_ANTENNA_DIFF 2 /* Num farmes difference in - tx to flip default recv - antenna */ +#define ATH_ANTENNA_DIFF 2 /* Num frames difference in + * tx to flip default recv + * antenna + */ struct ath_buf { /* FFXXX: convert both list types to TAILQ to save a field? */ - STAILQ_ENTRY(ath_buf) bf_list; + STAILQ_ENTRY(ath_buf) bf_list; #ifdef ATH_SUPERG_FF - TAILQ_ENTRY(ath_buf) bf_stagelist; /* fast-frame staging list */ + TAILQ_ENTRY(ath_buf) bf_stagelist; /* fast-frame staging list */ #endif - struct ath_desc *bf_desc; /* virtual addr of desc */ - dma_addr_t bf_daddr; /* physical addr of desc */ - struct sk_buff *bf_skb; /* skbuff for buf */ - dma_addr_t bf_skbaddr; /* physical addr of skb data */ - struct ieee80211_node *bf_node; /* pointer to the node */ - u_int32_t bf_status; /* status flags */ + struct ath_desc *bf_desc; /* virtual addr of desc */ + dma_addr_t bf_daddr; /* physical addr of desc */ + struct sk_buff *bf_skb; /* skbuff for buf */ + dma_addr_t bf_skbaddr; /* physical addr of skb data */ + struct ieee80211_node *bf_node; /* pointer to the node */ + u_int32_t bf_status; /* status flags */ #ifdef ATH_SUPERG_FF /* XXX: combine this with bf_skbaddr if it ever changes to accomodate * multiple segments. */ - u_int32_t bf_queueage; /* "age" of txq when this buffer placed on stageq */ - u_int16_t bf_numdesc; /* number of descs used */ - u_int16_t bf_flags; /* tx descriptor flags */ - dma_addr_t bf_skbaddrff[ATH_TXDESC-1]; /* extra addrs for ff */ + u_int32_t bf_queueage; /* "age" of txq when this buffer placed on stageq */ + u_int16_t bf_numdesc; /* number of descs used */ + u_int16_t bf_flags; /* tx descriptor flags */ + dma_addr_t bf_skbaddrff[ATH_TXDESC-1]; /* extra addrs for ff */ #endif }; @@ -340,8 +343,7 @@ * currently bf_status is the only one requires that * requires reset. */ -#define ATH_RXBUF_RESET(bf) \ - bf->bf_status=0 +#define ATH_RXBUF_RESET(bf) bf->bf_status=0 /* XXX: only managed for rx at the moment */ #define ATH_BUFSTATUS_DONE 0x00000001 /* hw processing complete, desc processed by hal */ @@ -350,11 +352,11 @@ * DMA state for tx/rx descriptors. */ struct ath_descdma { - const char* dd_name; - struct ath_desc *dd_desc; /* descriptors */ - dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */ - size_t dd_desc_len; /* size of dd_desc */ - struct ath_buf *dd_bufptr; /* associated buffers */ + const char *dd_name; + struct ath_desc *dd_desc; /* descriptors */ + dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */ + size_t dd_desc_len; /* size of dd_desc */ + struct ath_buf *dd_bufptr; /* associated buffers */ }; struct ath_hal; @@ -373,41 +375,40 @@ * hardware queue). */ struct ath_txq { - u_int axq_qnum; /* hardware q number */ - u_int32_t *axq_link; /* link ptr in last TX desc */ - STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ - spinlock_t axq_lock; /* lock on q and link */ - unsigned long axq_lockflags; /* intr state when must cli */ - u_int axq_depth; /* queue depth */ - u_int32_t axq_totalqueued;/* total ever queued */ - u_int axq_intrcnt; /* count to determine if descriptor - * should generate int on this txq. - */ + u_int axq_qnum; /* hardware q number */ + u_int32_t *axq_link; /* link ptr in last TX desc */ + STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ + spinlock_t axq_lock; /* lock on q and link */ + unsigned long axq_lockflags; /* intr state when must cli */ + u_int axq_depth; /* queue depth */ + u_int32_t axq_totalqueued; /* total ever queued */ + u_int axq_intrcnt; /* count to determine if descriptor + * should generate int on this txq. + */ /* * State for patching up CTS when bursting. */ - struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ + struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ /* * Staging queue for frames awaiting a fast-frame pairing. */ TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq; /* scratch compression buffer */ - char *axq_compbuf; /* scratch comp buffer */ - dma_addr_t axq_compbufp; /* scratch comp buffer (phys)*/ - u_int axq_compbufsz; /* scratch comp buffer size */ + char *axq_compbuf; /* scratch comp buffer */ + dma_addr_t axq_compbufp; /* scratch comp buffer (phys)*/ + u_int axq_compbufsz; /* scratch comp buffer size */ }; /* driver-specific vap state */ struct ath_vap { struct ieee80211vap av_vap; /* base class */ - int (*av_newstate)(struct ieee80211vap *, - enum ieee80211_state, int); + int (*av_newstate)(struct ieee80211vap *, enum ieee80211_state, int); /* XXX beacon state */ - struct ath_buf *av_bcbuf; /* beacon buffer */ + struct ath_buf *av_bcbuf; /* beacon buffer */ struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ - int av_bslot; /* beacon slot index */ - struct ath_txq av_mcastq; /* multicast transmit queue */ + int av_bslot; /* beacon slot index */ + struct ath_txq av_mcastq; /* multicast transmit queue */ u_int8_t av_dfswait_run; }; #define ATH_VAP(_v) ((struct ath_vap *)(_v)) @@ -458,171 +459,170 @@ #define BSTUCK_THRESH 3 /* # of stuck beacons before resetting NB: this is a guess*/ struct ath_softc { - struct ieee80211com sc_ic; /* NB: must be first */ - struct net_device* sc_dev; - struct semaphore sc_lock; /* dev-level lock */ + struct ieee80211com sc_ic; /* NB: must be first */ + struct net_device *sc_dev; + struct semaphore sc_lock; /* dev-level lock */ struct net_device_stats sc_devstats; /* device statistics */ - struct ath_stats sc_stats; /* private statistics */ - int sc_debug; - void (*sc_recv_mgmt)(struct ieee80211_node *, - struct sk_buff *, int, int, u_int32_t); - void (*sc_node_cleanup)(struct ieee80211_node *); - void (*sc_node_free)(struct ieee80211_node *); - void *sc_bdev; /* associated bus device */ - struct ath_hal *sc_ah; /* Atheros HAL */ - struct ath_ratectrl *sc_rc; /* tx rate control support */ - struct ath_tx99 *sc_tx99; /* tx99 support */ - void (*sc_setdefantenna)(struct ath_softc *, u_int); - unsigned int sc_invalid : 1, /* being detached */ - sc_mrretry : 1, /* multi-rate retry support */ - sc_softled : 1, /* enable LED gpio status */ - sc_splitmic: 1, /* split TKIP MIC keys */ - sc_needmib : 1, /* enable MIB stats intr */ - sc_hasdiversity : 1,/* rx diversity available */ - sc_diversity : 1, /* enable rx diversity */ - sc_olddiversity : 1, /* diversity setting before XR enable */ - sc_hasveol : 1, /* tx VEOL support */ - sc_hastpc : 1, /* per-packet TPC support */ - sc_dturbo : 1, /* dynamic turbo capable */ - sc_dturbo_switch: 1,/* turbo switch mode*/ - sc_dturbo_hold : 1,/* dynamic turbo hold state */ - sc_rate_recn_state : 1,/* dynamic turbo state recmded by ratectrl */ - sc_ignore_ar: 1,/* ignore AR during transision*/ - sc_ledstate: 1, /* LED on/off state */ - sc_blinking: 1, /* LED blink operation active */ - sc_beacons : 1, /* beacons running */ - sc_hasbmask: 1, /* bssid mask support */ - sc_mcastkey: 1, /* mcast key cache search */ - sc_hastsfadd:1, /* tsf adjust support */ - sc_scanning: 1, /* scanning active */ - sc_nostabeacons: 1, /* no beacons for station */ - sc_xrgrppoll: 1,/* xr group polls are active */ - sc_syncbeacon:1,/* sync/resync beacon timers */ - sc_hasclrkey: 1,/* CLR key supported */ - sc_devstopped:1,/* stopped due to of no tx bufs */ - sc_stagbeacons:1,/* use staggered beacons */ - sc_rtasksched:1, /* radar task is scheduled */ - sc_dfswait:1, /* waiting on channel for radar detect */ - sc_dfstest:1; /* Test timer in progress */ - /* rate tables */ - const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; - const HAL_RATE_TABLE *sc_currates; /* current rate table */ - const HAL_RATE_TABLE *sc_xr_rates; /* XR rate table */ - const HAL_RATE_TABLE *sc_half_rates; /* half rate table */ - const HAL_RATE_TABLE *sc_quarter_rates; /* quarter rate table */ - HAL_OPMODE sc_opmode; /* current hal operating mode */ - enum ieee80211_phymode sc_curmode; /* current phy mode */ - u_int16_t sc_curtxpow; /* current tx power limit */ - u_int16_t sc_curaid; /* current association id */ - HAL_CHANNEL sc_curchan; /* current h/w channel */ - u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; - u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ + struct ath_stats sc_stats; /* private statistics */ + int sc_debug; + void (*sc_recv_mgmt)(struct ieee80211_node *, struct sk_buff *, int, int, u_int32_t); + void (*sc_node_cleanup)(struct ieee80211_node *); + void (*sc_node_free)(struct ieee80211_node *); + void *sc_bdev; /* associated bus device */ + struct ath_hal *sc_ah; /* Atheros HAL */ + struct ath_ratectrl *sc_rc; /* tx rate control support */ + struct ath_tx99 *sc_tx99; /* tx99 support */ + void (*sc_setdefantenna)(struct ath_softc *, u_int); + unsigned int sc_invalid:1, /* being detached */ + sc_mrretry:1, /* multi-rate retry support */ + sc_softled:1, /* enable LED gpio status */ + sc_splitmic:1, /* split TKIP MIC keys */ + sc_needmib:1, /* enable MIB stats intr */ + sc_hasdiversity:1, /* rx diversity available */ + sc_diversity:1, /* enable rx diversity */ + sc_olddiversity:1, /* diversity setting before XR enable */ + sc_hasveol:1, /* tx VEOL support */ + sc_hastpc:1, /* per-packet TPC support */ + sc_dturbo:1, /* dynamic turbo capable */ + sc_dturbo_switch:1, /* turbo switch mode*/ + sc_dturbo_hold:1, /* dynamic turbo hold state */ + sc_rate_recn_state:1, /* dynamic turbo state recmded by ratectrl */ + sc_ignore_ar:1, /* ignore AR during transision*/ + sc_ledstate:1, /* LED on/off state */ + sc_blinking:1, /* LED blink operation active */ + sc_beacons:1, /* beacons running */ + sc_hasbmask:1, /* bssid mask support */ + sc_mcastkey:1, /* mcast key cache search */ + sc_hastsfadd:1, /* tsf adjust support */ + sc_scanning:1, /* scanning active */ + sc_nostabeacons:1, /* no beacons for station */ + sc_xrgrppoll:1, /* xr group polls are active */ + sc_syncbeacon:1, /* sync/resync beacon timers */ + sc_hasclrkey:1, /* CLR key supported */ + sc_devstopped:1, /* stopped due to of no tx bufs */ + sc_stagbeacons:1, /* use staggered beacons */ + sc_rtasksched:1, /* radar task is scheduled */ + sc_dfswait:1, /* waiting on channel for radar detect */ + sc_dfstest:1; /* Test timer in progress */ + /* rate tables */ + const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; + const HAL_RATE_TABLE *sc_currates; /* current rate table */ + const HAL_RATE_TABLE *sc_xr_rates; /* XR rate table */ + const HAL_RATE_TABLE *sc_half_rates; /* half rate table */ + const HAL_RATE_TABLE *sc_quarter_rates; /* quarter rate table */ + HAL_OPMODE sc_opmode; /* current hal operating mode */ + enum ieee80211_phymode sc_curmode; /* current phy mode */ + u_int16_t sc_curtxpow; /* current tx power limit */ + u_int16_t sc_curaid; /* current association id */ + HAL_CHANNEL sc_curchan; /* current h/w channel */ + u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; + u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ struct { - u_int8_t ieeerate; /* IEEE rate */ - u_int8_t flags; /* radiotap flags */ - u_int16_t ledon; /* softled on time */ - u_int16_t ledoff; /* softled off time */ + u_int8_t ieeerate; /* IEEE rate */ + u_int8_t flags; /* radiotap flags */ + u_int16_t ledon; /* softled on time */ + u_int16_t ledoff; /* softled off time */ } sc_hwmap[32]; /* h/w rate ix mappings */ - u_int8_t sc_minrateix; /* min h/w rate index */ - u_int8_t sc_protrix; /* protection rate index */ - u_int8_t sc_mcastantenna;/* Multicast antenna number */ - u_int8_t sc_txantenna; /* data tx antenna (fixed or auto) */ - u_int8_t sc_dfstest_ieeechan; /* IEEE channel number to return to after a dfs mute test */ - u_int32_t sc_dfstesttime; /* Time to stay off chan during dfs test */ - u_int16_t sc_nvaps; /* # of active virtual ap's */ - u_int8_t sc_nstavaps; /* # of active station vaps */ - u_int8_t sc_nmonvaps; /* # of monitor vaps */ - u_int8_t sc_nbcnvaps; /* # of vaps sending beacons */ - u_int sc_fftxqmin; /* aggregation threshold */ - HAL_INT sc_imask; /* interrupt mask copy */ - u_int sc_keymax; /* size of key cache */ - u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ - struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ - u_int8_t sc_bssidmask[IEEE80211_ADDR_LEN]; + u_int8_t sc_minrateix; /* min h/w rate index */ + u_int8_t sc_protrix; /* protection rate index */ + u_int8_t sc_mcastantenna; /* Multicast antenna number */ + u_int8_t sc_txantenna; /* data tx antenna (fixed or auto) */ + u_int8_t sc_dfstest_ieeechan; /* IEEE channel number to return to after a dfs mute test */ + u_int32_t sc_dfstesttime; /* Time to stay off chan during dfs test */ + u_int16_t sc_nvaps; /* # of active virtual ap's */ + u_int8_t sc_nstavaps; /* # of active station vaps */ + u_int8_t sc_nmonvaps; /* # of monitor vaps */ + u_int8_t sc_nbcnvaps; /* # of vaps sending beacons */ + u_int sc_fftxqmin; /* aggregation threshold */ + HAL_INT sc_imask; /* interrupt mask copy */ + u_int sc_keymax; /* size of key cache */ + u_int8_t sc_keymap[ATH_KEYBYTES]; /* key use bit map */ + struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ + u_int8_t sc_bssidmask[IEEE80211_ADDR_LEN]; - u_int sc_ledpin; /* GPIO pin for driving LED */ - u_int sc_ledon; /* pin setting for LED on */ - u_int sc_ledidle; /* idle polling interval */ - int sc_ledevent; /* time of last LED event */ - u_int8_t sc_rxrate; /* current rx rate for LED */ - u_int8_t sc_txrate; /* current tx rate for LED */ - u_int16_t sc_ledoff; /* off time for current blink */ - struct timer_list sc_ledtimer; /* led off timer */ - struct timer_list sc_dfswaittimer;/* dfs wait timer */ - struct timer_list sc_dfstesttimer;/* dfs mute test timer */ + u_int sc_ledpin; /* GPIO pin for driving LED */ + u_int sc_ledon; /* pin setting for LED on */ + u_int sc_ledidle; /* idle polling interval */ + int sc_ledevent; /* time of last LED event */ + u_int8_t sc_rxrate; /* current rx rate for LED */ + u_int8_t sc_txrate; /* current tx rate for LED */ + u_int16_t sc_ledoff; /* off time for current blink */ + struct timer_list sc_ledtimer; /* led off timer */ + struct timer_list sc_dfswaittimer; /* dfs wait timer */ + struct timer_list sc_dfstesttimer; /* dfs mute test timer */ - struct ATH_TQ_STRUCT sc_fataltq; /* fatal error intr tasklet */ + struct ATH_TQ_STRUCT sc_fataltq; /* fatal error intr tasklet */ - int sc_rxbufsize; /* rx size based on mtu */ - struct ath_descdma sc_rxdma; /* RX descriptors */ - ath_bufhead sc_rxbuf; /* receive buffer */ - struct ath_buf *sc_rxbufcur; /* current rx buffer */ - u_int32_t *sc_rxlink; /* link ptr in last RX desc */ - spinlock_t sc_rxbuflock; - unsigned long sc_rxbuflockflags; - struct ATH_TQ_STRUCT sc_rxtq; /* rx intr tasklet */ - struct ATH_TQ_STRUCT sc_rxorntq; /* rxorn intr tasklet */ - u_int8_t sc_defant; /* current default antenna */ - u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ - u_int16_t sc_cachelsz; /* cache line size */ + int sc_rxbufsize; /* rx size based on mtu */ + struct ath_descdma sc_rxdma; /* RX descriptors */ + ath_bufhead sc_rxbuf; /* receive buffer */ + struct ath_buf *sc_rxbufcur; /* current rx buffer */ + u_int32_t *sc_rxlink; /* link ptr in last RX desc */ + spinlock_t sc_rxbuflock; + unsigned long sc_rxbuflockflags; + struct ATH_TQ_STRUCT sc_rxtq; /* rx intr tasklet */ + struct ATH_TQ_STRUCT sc_rxorntq; /* rxorn intr tasklet */ + u_int8_t sc_defant; /* current default antenna */ + u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ + u_int16_t sc_cachelsz; /* cache line size */ - struct ath_descdma sc_txdma; /* TX descriptors */ - ath_bufhead sc_txbuf; /* transmit buffer */ - spinlock_t sc_txbuflock; /* txbuf lock */ - u_int sc_txqsetup; /* h/w queues setup */ - u_int sc_txintrperiod;/* tx interrupt batching */ - struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; - struct ath_txq *sc_ac2q[WME_NUM_AC]; /* WME AC -> h/w qnum */ - struct ATH_TQ_STRUCT sc_txtq; /* tx intr tasklet */ - u_int8_t sc_grppoll_str[GRPPOLL_RATE_STR_LEN]; - struct ath_descdma sc_bdma; /* beacon descriptors */ - ath_bufhead sc_bbuf; /* beacon buffers */ - u_int sc_bhalq; /* HAL q for outgoing beacons */ - u_int sc_bmisscount; /* missed beacon transmits */ - u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ - struct ath_txq *sc_cabq; /* tx q for cab frames */ - struct ath_txq sc_grpplq; /* tx q for XR group polls */ - struct ath_txq *sc_xrtxq; /* tx q for XR data */ - struct ath_descdma sc_grppolldma; /* TX descriptors for grppoll */ - ath_bufhead sc_grppollbuf; /* transmit buffers for grouppoll */ - u_int16_t sc_xrpollint; /* xr poll interval */ - u_int16_t sc_xrpollcount; /* xr poll count */ - struct ath_txq *sc_uapsdq; /* tx q for uapsd */ - struct ATH_TQ_STRUCT sc_bmisstq; /* bmiss intr tasklet */ - struct ATH_TQ_STRUCT sc_bstucktq; /* beacon stuck intr tasklet */ + struct ath_descdma sc_txdma; /* TX descriptors */ + ath_bufhead sc_txbuf; /* transmit buffer */ + spinlock_t sc_txbuflock; /* txbuf lock */ + u_int sc_txqsetup; /* h/w queues setup */ + u_int sc_txintrperiod; /* tx interrupt batching */ + struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; + struct ath_txq *sc_ac2q[WME_NUM_AC]; /* WME AC -> h/w qnum */ + struct ATH_TQ_STRUCT sc_txtq; /* tx intr tasklet */ + u_int8_t sc_grppoll_str[GRPPOLL_RATE_STR_LEN]; + struct ath_descdma sc_bdma; /* beacon descriptors */ + ath_bufhead sc_bbuf; /* beacon buffers */ + u_int sc_bhalq; /* HAL q for outgoing beacons */ + u_int sc_bmisscount; /* missed beacon transmits */ + u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ + struct ath_txq *sc_cabq; /* tx q for cab frames */ + struct ath_txq sc_grpplq; /* tx q for XR group polls */ + struct ath_txq *sc_xrtxq; /* tx q for XR data */ + struct ath_descdma sc_grppolldma; /* TX descriptors for grppoll */ + ath_bufhead sc_grppollbuf; /* transmit buffers for grouppoll */ + u_int16_t sc_xrpollint; /* xr poll interval */ + u_int16_t sc_xrpollcount; /* xr poll count */ + struct ath_txq *sc_uapsdq; /* tx q for uapsd */ + struct ATH_TQ_STRUCT sc_bmisstq; /* bmiss intr tasklet */ + struct ATH_TQ_STRUCT sc_bstucktq; /* beacon stuck intr tasklet */ enum { OK, /* no change needed */ UPDATE, /* update pending */ COMMIT /* beacon sent, commit change */ } sc_updateslot; /* slot time update fsm */ - int sc_slotupdate; /* slot to next advance fsm */ - struct ieee80211vap *sc_bslot[ATH_BCBUF];/* beacon xmit slots */ - int sc_bnext; /* next slot for beacon xmit */ + int sc_slotupdate; /* slot to next advance fsm */ + struct ieee80211vap *sc_bslot[ATH_BCBUF];/* beacon xmit slots */ + int sc_bnext; /* next slot for beacon xmit */ - struct timer_list sc_cal_ch; /* calibration timer */ - HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ - struct ATH_WORK_THREAD sc_radartask; /* Schedule task for DFS handling */ + struct timer_list sc_cal_ch; /* calibration timer */ + HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ + struct ATH_WORK_THREAD sc_radartask; /* Schedule task for DFS handling */ #ifdef CONFIG_SYSCTL - struct ctl_table_header *sc_sysctl_header; - struct ctl_table *sc_sysctls; + struct ctl_table_header *sc_sysctl_header; + struct ctl_table *sc_sysctls; #endif - u_int16_t sc_reapcount; /* # of tx buffers reaped after net dev stopped */ + u_int16_t sc_reapcount; /* # of tx buffers reaped after net dev stopped */ #ifdef ATH_SUPERG_DYNTURBO - struct timer_list sc_dturbo_switch_mode; /* AP scan timer */ - u_int32_t sc_dturbo_tcount; /* beacon intval count */ - u_int32_t sc_dturbo_hold_max; /* hold count before switching to base*/ - u_int16_t sc_dturbo_hold_count; /* hold count before switching to base*/ - u_int16_t sc_dturbo_turbo_tmin; /* min turbo count */ - u_int32_t sc_dturbo_bytes; /* bandwidth stats */ - u_int32_t sc_dturbo_base_tmin; /* min time in base */ - u_int32_t sc_dturbo_turbo_tmax; /* max time in turbo */ - u_int32_t sc_dturbo_bw_base; /* bandwidth threshold */ - u_int32_t sc_dturbo_bw_turbo; /* bandwidth threshold */ + struct timer_list sc_dturbo_switch_mode;/* AP scan timer */ + u_int32_t sc_dturbo_tcount; /* beacon intval count */ + u_int32_t sc_dturbo_hold_max; /* hold count before switching to base*/ + u_int16_t sc_dturbo_hold_count; /* hold count before switching to base*/ + u_int16_t sc_dturbo_turbo_tmin; /* min turbo count */ + u_int32_t sc_dturbo_bytes; /* bandwidth stats */ + u_int32_t sc_dturbo_base_tmin; /* min time in base */ + u_int32_t sc_dturbo_turbo_tmax; /* max time in turbo */ + u_int32_t sc_dturbo_bw_base; /* bandwidth threshold */ + u_int32_t sc_dturbo_bw_turbo; /* bandwidth threshold */ #endif - u_int sc_slottimeconf; /* manual override for slottime */ + u_int sc_slottimeconf; /* manual override for slottime */ }; typedef void (*ath_callback) (struct ath_softc *); @@ -651,17 +651,17 @@ #define ATH_LOCK(_sc) down(&(_sc)->sc_lock) #define ATH_UNLOCK(_sc) up(&(_sc)->sc_lock) -int ath_attach(u_int16_t, struct net_device *); -int ath_detach(struct net_device *); -void ath_resume(struct net_device *); -void ath_suspend(struct net_device *); -void ath_shutdown(struct net_device *); -irqreturn_t ath_intr(int irq, void *dev_id, struct pt_regs *regs); -int ath_ioctl_ethtool(struct ath_softc *sc, int cmd, void __user *addr); -void bus_read_cachesize(struct ath_softc *sc, u_int8_t *csz); +int ath_attach(u_int16_t, struct net_device *); +int ath_detach(struct net_device *); +void ath_resume(struct net_device *); +void ath_suspend(struct net_device *); +void ath_shutdown(struct net_device *); +irqreturn_t ath_intr(int, void *, struct pt_regs *); +int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); +void bus_read_cachesize(struct ath_softc *, u_int8_t *); #ifdef CONFIG_SYSCTL -void ath_sysctl_register(void); -void ath_sysctl_unregister(void); +void ath_sysctl_register(void); +void ath_sysctl_unregister(void); #endif /* CONFIG_SYSCTL */ /* Modified: trunk/ath_rate/amrr/amrr.h =================================================================== --- trunk/ath_rate/amrr/amrr.h 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath_rate/amrr/amrr.h 2006-02-06 16:03:21 UTC (rev 1441) @@ -42,22 +42,22 @@ /* per-device state */ struct amrr_softc { - struct ath_ratectrl arc; /* base state */ + struct ath_ratectrl arc; /* base state */ struct timer_list timer; /* periodic timer */ }; /* per-node state */ struct amrr_node { /* AMRR statistics for this node */ - u_int amn_tx_try0_cnt; - u_int amn_tx_try1_cnt; - u_int amn_tx_try2_cnt; - u_int amn_tx_try3_cnt; - u_int amn_tx_failure_cnt; + u_int amn_tx_try0_cnt; + u_int amn_tx_try1_cnt; + u_int amn_tx_try2_cnt; + u_int amn_tx_try3_cnt; + u_int amn_tx_failure_cnt; /* AMRR algorithm state for this node */ - u_int amn_success_threshold; - u_int amn_success; - u_int amn_recovery; + u_int amn_success_threshold; + u_int amn_success; + u_int amn_recovery; /* rate index et al. */ u_int8_t amn_tx_rix0; /* series 0 rate index */ u_int8_t amn_tx_rate0; /* series 0 h/w rate */ @@ -69,9 +69,9 @@ u_int8_t amn_tx_rate2sp; /* series 2 short preamble h/w rate */ u_int8_t amn_tx_rate3sp; /* series 3 short preamble h/w rate */ u_int8_t amn_tx_try0; /* series 0 try count */ - u_int amn_tx_try1; /* series 1 try count */ - u_int amn_tx_try2; /* series 2 try count */ - u_int amn_tx_try3; /* series 3 try count */ + u_int amn_tx_try1; /* series 1 try count */ + u_int amn_tx_try2; /* series 2 try count */ + u_int amn_tx_try3; /* series 3 try count */ }; #define ATH_NODE_AMRR(an) ((struct amrr_node *)&an[1]) #endif /* _DEV_ATH_RATE_AMRR_H */ Modified: trunk/ath_rate/onoe/onoe.h =================================================================== --- trunk/ath_rate/onoe/onoe.h 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath_rate/onoe/onoe.h 2006-02-06 16:03:21 UTC (rev 1441) @@ -44,26 +44,26 @@ /* per-device state */ struct onoe_softc { - struct ath_ratectrl arc; /* base state */ + struct ath_ratectrl arc; /* base state */ }; /* per-node state */ struct onoe_node { - u_int on_tx_ok; /* tx ok pkt */ - u_int on_tx_err; /* tx !ok pkt */ - u_int on_tx_retr; /* tx retry count */ - int on_tx_upper; /* tx upper rate req cnt */ - u_int8_t on_tx_rix0; /* series 0 rate index */ - u_int8_t on_tx_try0; /* series 0 try count */ - u_int8_t on_tx_rate0; /* series 0 h/w rate */ - u_int8_t on_tx_rate1; /* series 1 h/w rate */ - u_int8_t on_tx_rate2; /* series 2 h/w rate */ - u_int8_t on_tx_rate3; /* series 3 h/w rate */ - u_int8_t on_tx_rate0sp; /* series 0 short preamble h/w rate */ - u_int8_t on_tx_rate1sp; /* series 1 short preamble h/w rate */ - u_int8_t on_tx_rate2sp; /* series 2 short preamble h/w rate */ - u_int8_t on_tx_rate3sp; /* series 3 short preamble h/w rate */ - int on_nextcheck; /* time of next check for rate drop */ + u_int on_tx_ok; /* tx ok pkt */ + u_int on_tx_err; /* tx !ok pkt */ + u_int on_tx_retr; /* tx retry count */ + int on_tx_upper; /* tx upper rate req cnt */ + u_int8_t on_tx_rix0; /* series 0 rate index */ + u_int8_t on_tx_try0; /* series 0 try count */ + u_int8_t on_tx_rate0; /* series 0 h/w rate */ + u_int8_t on_tx_rate1; /* series 1 h/w rate */ + u_int8_t on_tx_rate2; /* series 2 h/w rate */ + u_int8_t on_tx_rate3; /* series 3 h/w rate */ + u_int8_t on_tx_rate0sp; /* series 0 short preamble h/w rate */ + u_int8_t on_tx_rate1sp; /* series 1 short preamble h/w rate */ + u_int8_t on_tx_rate2sp; /* series 2 short preamble h/w rate */ + u_int8_t on_tx_rate3sp; /* series 3 short preamble h/w rate */ + int on_nextcheck; /* time of next check for rate drop */ }; #define ATH_NODE_ONOE(an) ((struct onoe_node *)&an[1]) #endif /* _DEV_ATH_RATE_ONOE_H */ Modified: trunk/ath_rate/sample/sample.c =================================================================== --- trunk/ath_rate/sample/sample.c 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath_rate/sample/sample.c 2006-02-06 16:03:21 UTC (rev 1441) @@ -146,7 +146,110 @@ return -1; } +/* + * Calculate the transmit duration of a frame. + */ +static unsigned +calc_usecs_unicast_packet(struct ath_softc *sc, int length, + int rix, int short_retries, int long_retries) +{ + const HAL_RATE_TABLE *rt = sc->sc_currates; + int rts, cts; + + unsigned t_slot = 20; + unsigned t_difs = 50; + unsigned t_sifs = 10; + struct ieee80211com *ic = &sc->sc_ic; + int tt = 0; + int x = 0; + int cw = WIFI_CW_MIN; + int cix = rt->info[rix].controlRate; + KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); + if (!rt->info[rix].rateKbps) { + printk(KERN_WARNING "rix %d (%d) bad ratekbps %d mode %u\n", + rix, rt->info[rix].dot11Rate, + rt->info[rix].rateKbps, + sc->sc_curmode); + + return 0; + } + /* + * XXX getting mac/phy level timings should be fixed for turbo + * rates, and there is probably a way to get this from the + * hal... + */ + switch (rt->info[rix].phy) { + case IEEE80211_T_OFDM: + t_slot = 9; + t_sifs = 16; + t_difs = 28; + /* fall through */ + case IEEE80211_T_TURBO: + t_slot = 9; + t_sifs = 8; + t_difs = 28; + break; + case IEEE80211_T_DS: + /* fall through to default */ + default: + /* pg 205 ieee.802.11.pdf */ + t_slot = 20; + t_difs = 50; + t_sifs = 10; + } + + rts = cts = 0; + + if ((ic->ic_flags & IEEE80211_F_USEPROT) && + rt->info[rix].phy == IEEE80211_T_OFDM) { + if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) + rts = 1; + else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) + cts = 1; + + cix = rt->info[sc->sc_protrix].controlRate; + } + + if (0 /*length > ic->ic_rtsthreshold */) + rts = 1; + + if (rts || cts) { + int ctsrate = rt->info[cix].rateCode; + int ctsduration = 0; + + if (!rt->info[cix].rateKbps) { + printk(KERN_WARNING "cix %d (%d) bad ratekbps %d mode %u\n", + cix, rt->info[cix].dot11Rate, + rt->info[cix].rateKbps, + sc->sc_curmode); + return 0; + } + + + ctsrate |= rt->info[cix].shortPreamble; + if (rts) /* SIFS + CTS */ + ctsduration += rt->info[cix].spAckDuration; + + ctsduration += ath_hal_computetxtime(sc->sc_ah, + rt, length, rix, AH_TRUE); + + if (cts) /* SIFS + ACK */ + ctsduration += rt->info[cix].spAckDuration; + + tt += (short_retries + 1) * ctsduration; + } + tt += t_difs; + tt += (long_retries+1)*(t_sifs + rt->info[rix].spAckDuration); + tt += (long_retries+1)*ath_hal_computetxtime(sc->sc_ah, rt, length, + rix, AH_TRUE); + for (x = 0; x <= short_retries + long_retries; x++) { + cw = MIN(WIFI_CW_MAX, (cw + 1) * 2); + tt += (t_slot * cw / 2); + } + return tt; +} + void ath_rate_node_init(struct ath_softc *sc, struct ath_node *an) { Modified: trunk/ath_rate/sample/sample.h =================================================================== --- trunk/ath_rate/sample/sample.h 2006-02-05 09:11:03 UTC (rev 1440) +++ trunk/ath_rate/sample/sample.h 2006-02-06 16:03:21 UTC (rev 1441) @@ -44,9 +44,9 @@ /* per-device state */ struct sample_softc { - struct ath_ratectrl arc; /* base state */ - int ath_smoothing_rate; /* ewma percentage (out of 100) */ - int ath_sample_rate; /* send a different bit-rate 1/X packets */ + struct ath_ratectrl arc; /* base state */ + int ath_smoothing_rate; /* ewma percentage (out of 100) */ + int ath_sample_rate; /* send a different bit-rate 1/X packets */ #ifdef CONFIG_SYSCTL struct ctl_table_header *sysctl_header; @@ -70,7 +70,7 @@ int tries; int total_packets; int packets_acked; - unsigned perfect_tx_time; /* transmit time for 0 retries */ + unsigned perfect_tx_time; /* transmit time for 0 retries */ int last_tx; }; @@ -119,175 +119,72 @@ /* * tx_control_0 */ - u_int32_t frame_len:12; - u_int32_t reserved_12_15:4; - u_int32_t xmit_power:6; - u_int32_t rts_cts_enable:1; - u_int32_t veol:1; - u_int32_t clear_dest_mask:1; - u_int32_t ant_mode_xmit:4; - u_int32_t inter_req:1; - u_int32_t encrypt_key_valid:1; - u_int32_t cts_enable:1; + u_int32_t frame_len:12; + u_int32_t reserved_12_15:4; + u_int32_t xmit_power:6; + u_int32_t rts_cts_enable:1; + u_int32_t veol:1; + u_int32_t clear_dest_mask:1; + u_int32_t ant_mode_xmit:4; + u_int32_t inter_req:1; + u_int32_t encrypt_key_valid:1; + u_int32_t cts_enable:1; /* * tx_control_1 */ - u_int32_t buf_len:12; - u_int32_t more:1; - u_int32_t encrypt_key_index:7; - u_int32_t frame_type:4; - u_int32_t no_ack:1; - u_int32_t comp_proc:2; - u_int32_t comp_iv_len:2; - u_int32_t comp_icv_len:2; - u_int32_t reserved_31:1; + u_int32_t buf_len:12; + u_int32_t more:1; + u_int32_t encrypt_key_index:7; + u_int32_t frame_type:4; + u_int32_t no_ack:1; + u_int32_t comp_proc:2; + u_int32_t comp_iv_len:2; + u_int32_t comp_icv_len:2; + u_int32_t reserved_31:1; /* * tx_control_2 */ - u_int32_t rts_duration:15; - u_int32_t duration_update_enable:1; - u_int32_t xmit_tries0:4; - u_int32_t xmit_tries1:4; - u_int32_t xmit_tries2:4; - u_int32_t xmit_tries3:4; + u_int32_t rts_duration:15; + u_int32_t duration_update_enable:1; + u_int32_t xmit_tries0:4; + u_int32_t xmit_tries1:4; + u_int32_t xmit_tries2:4; + u_int32_t xmit_tries3:4; /* * tx_control_3 */ - u_int32_t xmit_rate0:5; - u_int32_t xmit_rate1:5; - u_int32_t xmit_rate2:5; - u_int32_t xmit_rate3:5; - u_int32_t rts_cts_rate:5; - u_int32_t ... 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