Attached is an enhanced version of makefile.linux
- Resolved the *.c/*.cpp source file list to object list question
- Added a TOOLPREFIX variable for targeting a specific compiler
- Added an install target, with support for standard DESTDIR and PREFIX variables
- Added an uninstall target
- Added variables to control configuration (ENABLE_PNG, ENABLE_TILE_RENDERING, ENABLE_OFFSCREEN_RENDERING, ENABLE_TEST_GUI), to reduce the need for editing the makefile. By default, all configuration variable values are set to "Yes"
Make variable values may be set on the make command line. For example--
$ make TOOLPREFIX=i486-pc-linux-gnu-
or
$ make ENABLE_TEST_GUI=No
or
$ make DESTDIR=/tmp/dist/package PREFIX=/usr install
etc.
Thank you!
makefile.linux
I replaced the old makefile.linux with this one in CVS. It should make it into the 1.2.4 release.
Many people use compilers that are not just variants of GCC (for example, llvm/clang is quite popular). The above patch assumes that people will only ever want to use variants of gcc. Also, in *nix it is a widely accepted convention that people can just set CC to whatever compiler they want (via environment variables), TOOLPREFIX is not a common thing.
In addition, people's C++ compilers are not necessarily also their C compilers, so CXX shouldn't be strictly tied to CC.
Please consider the following:
(The ?= operator only sets the variable if it is not already set.)
Last edit: Jean-Philippe Ouellet 2013-09-14
It is not uncommon in scenarios such as cross-compilation setups and is actually quite useful in like cases.
If you need a different compiler for a different architecture, you can specify it via CC. Also, not all things end in gcc, so it doesn't make sense to assume so in the makefile. I sometimes need to use intel's compiler (icc) to cross compile things, note how it doesn't end in gcc.
Also, the preferred way (with gcc) to specify target-architecture-specific things is via -m, not with specially named invocations.
No, TOOLPREFIX is for more than just the compiler.
Last edit: mesheets 2013-09-14
Ah, that makes sense. I was not aware. Thanks.
Still though, why the forced gcc suffix?
How about the following:
CC?=gcc
CXX?=$(CC)
CC=$(TOOLPREFIX)$(CC)
CXX=$(TOOLPREFIX)$(CXX)
Last edit: mesheets 2013-09-14
^ +1
Ok, I hope ^ +1 means "go for it" because I checked in the tweaked makefile.linux. Maybe I'll try and cross compile it for ARM to see if that really works.