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[Jikesrvm-commits] SF.net SVN: jikesrvm: [12345] rvmroot/trunk/rvm/src
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From: <cap...@us...> - 2007-05-26 02:01:44
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Revision: 12345
http://svn.sourceforge.net/jikesrvm/?rev=12345&view=rev
Author: captain5050
Date: 2007-05-25 19:01:42 -0700 (Fri, 25 May 2007)
Log Message:
-----------
Remove accumulate LIR instructions.
Modified Paths:
--------------
rvmroot/trunk/rvm/src/org/jikesrvm/compilers/opt/ia32/OPT_ConvertALUOperators.java
rvmroot/trunk/rvm/src-generated/opt-ir/ia32/InstructionFormatList.dat
rvmroot/trunk/rvm/src-generated/opt-ir/ia32/OperatorList.dat
Modified: rvmroot/trunk/rvm/src/org/jikesrvm/compilers/opt/ia32/OPT_ConvertALUOperators.java
===================================================================
--- rvmroot/trunk/rvm/src/org/jikesrvm/compilers/opt/ia32/OPT_ConvertALUOperators.java 2007-05-26 00:39:01 UTC (rev 12344)
+++ rvmroot/trunk/rvm/src/org/jikesrvm/compilers/opt/ia32/OPT_ConvertALUOperators.java 2007-05-26 02:01:42 UTC (rev 12345)
@@ -18,7 +18,6 @@
import org.jikesrvm.compilers.opt.OPT_OptimizingCompilerException;
import org.jikesrvm.compilers.opt.OPT_Simplifier;
import org.jikesrvm.compilers.opt.ir.Binary;
-import org.jikesrvm.compilers.opt.ir.BinaryAcc;
import org.jikesrvm.compilers.opt.ir.CondMove;
import org.jikesrvm.compilers.opt.ir.Move;
import org.jikesrvm.compilers.opt.ir.OPT_IR;
@@ -32,7 +31,6 @@
import org.jikesrvm.compilers.opt.ir.OPT_Register;
import org.jikesrvm.compilers.opt.ir.OPT_RegisterOperand;
import org.jikesrvm.compilers.opt.ir.Unary;
-import org.jikesrvm.compilers.opt.ir.UnaryAcc;
import org.vmmagic.pragma.NoOptCompile;
/**
@@ -102,6 +100,7 @@
private static final boolean OPTIMIZE = true;
+ @Override
public final String getName() { return "ConvertALUOps"; }
/**
@@ -110,10 +109,12 @@
* @param ir not used
* @return this
*/
+ @Override
public OPT_CompilerPhase newExecution(OPT_IR ir) {
return this;
}
+ @Override
public final void perform(OPT_IR ir) {
// Calling OPT_Simplifier.simplify ensures that the instruction is
// in normalized form. This reduces the number of cases we have to
@@ -140,109 +141,48 @@
// Reverse pass over instructions supports simple live analysis.
for (OPT_Instruction next, s = ir.lastInstructionInCodeOrder(); s != null; s = next) {
next = s.prevInstructionInCodeOrder();
+
+ switch(s.getOpcode()) {
+ case BOOLEAN_NOT_opcode: break;
+ case REF_NOT_opcode: s.operator = INT_NOT; break;
+ case INT_NOT_opcode: break;
+ case LONG_NOT_opcode: break;
- switch (s.getOpcode()) {
- case BOOLEAN_NOT_opcode:
- unary(s, BOOLEAN_NOT_ACC, ir);
- break;
+ case REF_ADD_opcode: s.operator = INT_ADD; break;
+ case INT_ADD_opcode: break;
+ case REF_SUB_opcode: s.operator = INT_SUB; break;
+ case INT_SUB_opcode: break;
+ case REF_NEG_opcode: s.operator = INT_NEG; break;
+ case INT_NEG_opcode: break;
+ case LONG_NEG_opcode: break;
+ case REF_AND_opcode: s.operator = INT_AND; break;
+ case INT_AND_opcode: break;
+ case REF_OR_opcode: s.operator = INT_OR; break;
+ case INT_OR_opcode: break;
+ case REF_XOR_opcode: s.operator = INT_XOR; break;
+ case INT_XOR_opcode: break;
+ case LONG_AND_opcode: break;
+ case LONG_OR_opcode: break;
+ case LONG_XOR_opcode: break;
- case REF_ADD_opcode:
- commutative(s, INT_ADD_ACC, ir);
- break;
- case INT_ADD_opcode:
- commutative(s, INT_ADD_ACC, ir);
- break;
- case REF_SUB_opcode:
- noncommutative(s, INT_SUB_ACC, ir);
- break;
- case INT_SUB_opcode:
- noncommutative(s, INT_SUB_ACC, ir);
- break;
- case INT_MUL_opcode:
- commutative(s, INT_MUL_ACC, ir);
- break;
- case REF_SHL_opcode:
- noncommutative(s, INT_SHL_ACC, ir);
- break;
- case INT_SHL_opcode:
- noncommutative(s, INT_SHL_ACC, ir);
- break;
- case REF_SHR_opcode:
- noncommutative(s, INT_SHR_ACC, ir);
- break;
- case INT_SHR_opcode:
- noncommutative(s, INT_SHR_ACC, ir);
- break;
- case REF_USHR_opcode:
- noncommutative(s, INT_USHR_ACC, ir);
- break;
- case INT_USHR_opcode:
- noncommutative(s, INT_USHR_ACC, ir);
- break;
- case REF_AND_opcode:
- commutative(s, INT_AND_ACC, ir);
- break;
- case INT_AND_opcode:
- commutative(s, INT_AND_ACC, ir);
- break;
- case REF_OR_opcode:
- commutative(s, INT_OR_ACC, ir);
- break;
- case INT_OR_opcode:
- commutative(s, INT_OR_ACC, ir);
- break;
- case REF_XOR_opcode:
- commutative(s, INT_XOR_ACC, ir);
- break;
- case INT_XOR_opcode:
- commutative(s, INT_XOR_ACC, ir);
- break;
- case INT_NEG_opcode:
- unary(s, INT_NEG_ACC, ir);
- break;
- case REF_NEG_opcode:
- unary(s, INT_NEG_ACC, ir);
- break;
- case REF_NOT_opcode:
- unary(s, INT_NOT_ACC, ir);
- break;
- case INT_NOT_opcode:
- unary(s, INT_NOT_ACC, ir);
- break;
+ case REF_SHL_opcode: s.operator = INT_SHL; break;
+ case INT_SHL_opcode: break;
+ case REF_SHR_opcode: s.operator = INT_SHR; break;
+ case INT_SHR_opcode: break;
+ case REF_USHR_opcode: s.operator = INT_USHR; break;
+ case INT_USHR_opcode: break;
+
+ case LONG_SHL_opcode: break;
+ case LONG_SHR_opcode: break;
+ case LONG_USHR_opcode: break;
+
case LONG_ADD_opcode:
- commutative(s, LONG_ADD_ACC, ir);
break;
case LONG_SUB_opcode:
- noncommutative(s, LONG_SUB_ACC, ir);
break;
case LONG_MUL_opcode:
- commutative(s, LONG_MUL_ACC, ir);
break;
- case LONG_SHL_opcode:
- noncommutative(s, LONG_SHL_ACC, ir);
- break;
- case LONG_SHR_opcode:
- noncommutative(s, LONG_SHR_ACC, ir);
- break;
- case LONG_USHR_opcode:
- noncommutative(s, LONG_USHR_ACC, ir);
- break;
- case LONG_AND_opcode:
- commutative(s, LONG_AND_ACC, ir);
- break;
- case LONG_OR_opcode:
- commutative(s, LONG_OR_ACC, ir);
- break;
- case LONG_XOR_opcode:
- commutative(s, LONG_XOR_ACC, ir);
- break;
- case LONG_NEG_opcode:
- unary(s, LONG_NEG_ACC, ir);
- break;
- case LONG_NOT_opcode:
- unary(s, LONG_NOT_ACC, ir);
- break;
// BURS doesn't really care, so consolidate to reduce rule space
case BOOLEAN_CMP_ADDR_opcode:
@@ -376,226 +316,6 @@
}
}
- private void commutative(OPT_Instruction s, OPT_Operator opCode, OPT_IR ir) {
- OPT_RegisterOperand result = Binary.getClearResult(s);
- OPT_Operand op1 = Binary.getClearVal1(s);
- OPT_Operand op2 = Binary.getClearVal2(s);
-
- // Handle the easy cases of avoiding useless moves.
- if (result.similar(op1)) {
- OPT_DefUse.removeUse(op1.asRegister());
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(result);
- BinaryAcc.mutate(s, opCode, result, op2);
- return;
- }
- if (result.similar(op2)) {
- OPT_DefUse.removeUse(op2.asRegister());
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(result);
- BinaryAcc.mutate(s, opCode, result, op1);
- return;
- }
-
- // attempt to detect additional cases using simple liveness and DU info
- if (OPTIMIZE) {
- if (op1.isRegister()) {
- OPT_RegisterOperand rop1 = op1.asRegister();
- if (!rop1.register.spansBasicBlock() && isDead(rop1.register)) {
- if (result.register.isSSA() && !result.register.spansBasicBlock() && rop1.register.isSSA()) {
- OPT_DefUse.removeDef(result);
- OPT_DefUse.removeUse(rop1);
- OPT_DefUse.recordDefUse(rop1);
- OPT_DefUse.mergeRegisters(ir, rop1.register, result.register);
- rop1.register.putSSA(false);
- BinaryAcc.mutate(s, opCode, rop1, op2);
- return;
- } else {
- OPT_DefUse.removeDef(result);
- OPT_DefUse.removeUse(rop1);
- OPT_DefUse.recordDefUse(rop1);
- BinaryAcc.mutate(s, opCode, rop1, op2);
- OPT_Instruction move = Move.create(getMoveOp(result.type), result, rop1.copy());
- OPT_DefUse.updateDUForNewInstruction(move);
- s.insertAfter(move);
- return;
- }
- }
- }
- if (op2.isRegister()) {
- OPT_RegisterOperand rop2 = op2.asRegister();
- if (!rop2.register.spansBasicBlock() && isDead(rop2.register)) {
- if (result.register.isSSA() && !result.register.spansBasicBlock() && rop2.register.isSSA()) {
- OPT_DefUse.removeUse(rop2);
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(rop2);
- OPT_DefUse.mergeRegisters(ir, rop2.register, result.register);
- rop2.register.putSSA(false);
- BinaryAcc.mutate(s, opCode, rop2, op1);
- return;
- } else {
- OPT_DefUse.removeDef(result);
- OPT_DefUse.removeUse(rop2);
- OPT_DefUse.recordDefUse(rop2);
- BinaryAcc.mutate(s, opCode, rop2, op1);
- OPT_Instruction move = Move.create(getMoveOp(result.type), result, rop2.copy());
- OPT_DefUse.updateDUForNewInstruction(move);
- s.insertAfter(move);
- return;
- }
- }
- }
- }
-
- // Sigh, need some kind of move instruction
- OPT_Instruction move = Move.create(getMoveOp(result.type), result.copyRO(), op1.copy());
- OPT_DefUse.updateDUForNewInstruction(move);
- s.insertBefore(move);
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(result);
- if (op1.isRegister()) {
- OPT_DefUse.removeUse(op1.asRegister());
- }
- BinaryAcc.mutate(s, opCode, result, op2);
- }
-
- private void noncommutative(OPT_Instruction s, OPT_Operator opCode, OPT_IR ir) {
- OPT_RegisterOperand result = Binary.getClearResult(s);
- OPT_Operand op1 = Binary.getClearVal1(s);
- OPT_Operand op2 = Binary.getClearVal2(s);
-
- // Handle the easy cases of avoiding useless moves.
- if (result.similar(op1)) {
- OPT_DefUse.removeUse(op1.asRegister());
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(result);
- BinaryAcc.mutate(s, opCode, result, op2);
- return;
- }
-
- // attempt to detect additional cases using simple liveness and DU info
- if (OPTIMIZE) {
- if (op1.isRegister()) {
- OPT_RegisterOperand rop1 = op1.asRegister();
- if (!rop1.register.spansBasicBlock() && isDead(rop1.register)) {
- if (result.register.isSSA() && !result.register.spansBasicBlock() && rop1.register.isSSA()) {
- OPT_DefUse.removeUse(rop1);
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(rop1);
- OPT_DefUse.mergeRegisters(ir, rop1.register, result.register);
- rop1.register.putSSA(false);
- BinaryAcc.mutate(s, opCode, rop1, op2);
- return;
- } else {
- OPT_DefUse.removeDef(result);
- OPT_DefUse.removeUse(rop1);
- OPT_DefUse.recordDefUse(rop1);
- BinaryAcc.mutate(s, opCode, rop1, op2);
- OPT_Instruction move = Move.create(getMoveOp(result.type), result, rop1.copy());
- OPT_DefUse.updateDUForNewInstruction(move);
- s.insertAfter(move);
- return;
- }
- }
- }
- }
-
- // Sigh need some move instructions after all.
- if (result.similar(op2)) {
- similarNonCommutative(s, opCode, ir, result, op1, op2);
- } else {
- OPT_Instruction move = Move.create(getMoveOp(result.type), result.copyRO(), op1.copy());
- OPT_DefUse.updateDUForNewInstruction(move);
- s.insertBefore(move);
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(result);
- if (op1.isRegister()) {
- OPT_DefUse.removeUse(op1.asRegister());
- }
- BinaryAcc.mutate(s, opCode, result, op2);
- }
- }
-
- @NoOptCompile
- // this code is pulled out and baseline compiled to work around a bug (see bug track 1626523)
- private void similarNonCommutative(OPT_Instruction s, OPT_Operator opCode, OPT_IR ir, OPT_RegisterOperand result,
- OPT_Operand op1, OPT_Operand op2) {
- OPT_RegisterOperand tmp = ir.regpool.makeTemp(op1);
- OPT_Instruction move = Move.create(getMoveOp(tmp.type), tmp.copyRO(), op1.copy());
- s.insertBefore(move);
- OPT_DefUse.updateDUForNewInstruction(move);
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(tmp);
- if (op1.isRegister()) {
- OPT_DefUse.removeUse(op1.asRegister());
- }
- BinaryAcc.mutate(s, opCode, tmp, op2);
- move = Move.create(getMoveOp(tmp.type), result.copyRO(), tmp.copyRO());
- s.insertAfter(move);
- OPT_DefUse.updateDUForNewInstruction(move);
- }
-
- private void unary(OPT_Instruction s, OPT_Operator opCode, OPT_IR ir) {
- OPT_RegisterOperand result = Unary.getClearResult(s);
- OPT_Operand op1 = Unary.getClearVal(s);
-
- // Handle the easy cases of avoiding useless moves.
- if (result.similar(op1)) {
- OPT_DefUse.removeUse(op1.asRegister());
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(result);
- UnaryAcc.mutate(s, opCode, result);
- return;
- }
-
- // attempt to detect additional cases using simple liveness and DU info
- if (OPTIMIZE) {
- if (op1.isRegister()) {
- OPT_RegisterOperand rop1 = op1.asRegister();
- if (!rop1.register.spansBasicBlock() && isDead(rop1.register)) {
- if (result.register.isSSA() && !result.register.spansBasicBlock() && rop1.register.isSSA()) {
- OPT_DefUse.removeUse(rop1);
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(rop1);
- OPT_DefUse.mergeRegisters(ir, rop1.register, result.register);
- rop1.register.putSSA(false);
- UnaryAcc.mutate(s, opCode, rop1);
- return;
- } else {
- OPT_DefUse.removeDef(result);
- OPT_DefUse.removeUse(rop1);
- OPT_DefUse.recordDefUse(rop1);
- UnaryAcc.mutate(s, opCode, rop1);
- OPT_Instruction move = Move.create(getMoveOp(result.type), result, rop1.copy());
- OPT_DefUse.updateDUForNewInstruction(move);
- s.insertAfter(move);
- return;
- }
- }
- }
- }
-
- // Sigh, need the move instruction before op.
- OPT_Instruction move = Move.create(getMoveOp(result.type), result.copyRO(), op1.copy());
- OPT_DefUse.updateDUForNewInstruction(move);
- s.insertBefore(move);
- OPT_DefUse.removeDef(result);
- OPT_DefUse.recordDefUse(result);
- if (op1.isRegister()) {
- OPT_DefUse.removeUse(op1.asRegister());
- }
- UnaryAcc.mutate(s, opCode, result);
- }
-
- private static OPT_Operator getMoveOp(VM_TypeReference t) {
- OPT_Operator op = OPT_IRTools.getMoveOp(t);
- if (op == REF_MOVE) {
- return INT_MOVE;
- } else {
- return op;
- }
- }
-
// Use the scratch field of the register to record
// dead/live for local live analysis.
private static void markDead(OPT_Register r) {
@@ -606,10 +326,6 @@
r.scratch = 1;
}
- private static boolean isDead(OPT_Register r) {
- return r.scratch == 0;
- }
-
@SuppressWarnings("unused")
// completes the set
private static boolean isLive(OPT_Register r) {
Modified: rvmroot/trunk/rvm/src-generated/opt-ir/ia32/InstructionFormatList.dat
===================================================================
--- rvmroot/trunk/rvm/src-generated/opt-ir/ia32/InstructionFormatList.dat 2007-05-26 00:39:01 UTC (rev 12344)
+++ rvmroot/trunk/rvm/src-generated/opt-ir/ia32/InstructionFormatList.dat 2007-05-26 02:01:42 UTC (rev 12345)
@@ -21,18 +21,6 @@
# use PLURAL if NAME"s" is not plural for NAME
VARSIG
-# Accumulating Binary: result = result op value
-BinaryAcc
-0 1 1
-"DU Result OPT_RegisterOperand" "U Value OPT_Operand"
-
-
-# Accumulating Unary: result = op result
-UnaryAcc
-0 1 0
-"DU Result OPT_RegisterOperand"
-
-
# backend support for tableswitch
MIR_LowTableSwitch
0 1 0 2 U -1
Modified: rvmroot/trunk/rvm/src-generated/opt-ir/ia32/OperatorList.dat
===================================================================
--- rvmroot/trunk/rvm/src-generated/opt-ir/ia32/OperatorList.dat 2007-05-26 00:39:01 UTC (rev 12344)
+++ rvmroot/trunk/rvm/src-generated/opt-ir/ia32/OperatorList.dat 2007-05-26 02:01:42 UTC (rev 12345)
@@ -68,178 +68,6 @@
########################################
-# We begin with 2/1-operand (accumulating) variants of the 3/2-operand
-# ALU operators
-# These operators are shared by the IA32 and 390 backends.
-########################################
-# Add a (register/constant) integer operand to the register operand result
-INT_ADD_ACC
-BinaryAcc
-none
-
-
-
-# Add a (register/constant) long operand to the register operand result
-LONG_ADD_ACC
-BinaryAcc
-none
-
-
-
-# Subtract a (register/constant) int operand from the register operand result
-INT_SUB_ACC
-BinaryAcc
-none
-
-
-
-# Subtract a (register/constant) long operand from the register operand result
-LONG_SUB_ACC
-BinaryAcc
-none
-
-
-
-# Multiply the register operand result by a (register/constant) int operand
-INT_MUL_ACC
-BinaryAcc
-none
-
-
-
-# Multiply the register operand result by a (register/constant) long operand
-LONG_MUL_ACC
-BinaryAcc
-none
-
-
-
-# Negate the result register operand (an integer)
-INT_NEG_ACC
-UnaryAcc
-none
-
-
-
-# Negate the result register operand (a long)
-LONG_NEG_ACC
-UnaryAcc
-none
-
-
-
-# Shift logical left the (int) result register operand by the amount specified
-# by the (register/constant) int operand
-INT_SHL_ACC
-BinaryAcc
-none
-
-
-
-# Shift logical left the (long) result register operand by the amount specified
-# by the (register/constant) int operand
-LONG_SHL_ACC
-BinaryAcc
-none
-
-
-
-# Shift arithmetic right the (int) result register operand by the amount specified
-# by the (register/constant) int operand
-INT_SHR_ACC
-BinaryAcc
-none
-
-
-
-# Shift arithmetic right the (long) result register operand by the amount specified
-# by the (register/constant) int operand
-LONG_SHR_ACC
-BinaryAcc
-none
-
-
-
-# Shift logical right the (int) result register operand by the amount specified
-# by the (register/constant) int operand
-INT_USHR_ACC
-BinaryAcc
-none
-
-
-
-# Shift logical right the (long) result register operand by the amount specified
-# by the (register/constant) int operand
-LONG_USHR_ACC
-BinaryAcc
-none
-
-
-
-# Bitwise and a (register/constant) int operand into the register operand result
-INT_AND_ACC
-BinaryAcc
-none
-
-
-
-# Bitwise and a (register/constant) long operand into the register operand result
-LONG_AND_ACC
-BinaryAcc
-none
-
-
-
-# Bitwise or a (register/constant) int operand into the register operand result
-INT_OR_ACC
-BinaryAcc
-none
-
-
-
-# Bitwise or a (register/constant) long operand into the register operand result
-LONG_OR_ACC
-BinaryAcc
-none
-
-
-
-# Bitwise xor a (register/constant) int operand into the register operand result
-INT_XOR_ACC
-BinaryAcc
-none
-
-
-
-# Bitwise complement the (int) register operand result
-INT_NOT_ACC
-UnaryAcc
-none
-
-
-
-# Bitwise complement the (long) register operand result
-LONG_NOT_ACC
-UnaryAcc
-none
-
-
-
-# Bitwise xor a (register/constant) long operand into the a register operand result
-LONG_XOR_ACC
-BinaryAcc
-none
-
-
-
-# Boolean complement the (int) register operand result
-BOOLEAN_NOT_ACC
-UnaryAcc
-none
-
-
-
-########################################
# Next comes the machine specific HIR/LIR instructions.
########################################
####################
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