[Jikesrvm-core] Problem at runtime with a inserted instruction

[Isabella T. <is...@mi...>]

Hi,

Writing different values to different adresses works with the optimizing 
compiler, but when I write lots of times the same value on the same 
adress, the execution fails with exceptions, I've posted before. So, I 
guess, there is something going wrong when the compiler tries to 
optimize the operands.
As I see in 
jikesrvm/rvm/src/vm/compilers/optimizing/ir/conversions/lir2mir/OPT_BURS_MemOp_Helpers.java
the function MO_D is used, when the base register and offset are 
determined to be integer constants and so a MemoryOperand without base 
register is created and the direct address is calculated (hope, I am 
right). See below

In 
jikesrvm/rvm/src/vm/compilers/optimizing/ir/instruction/operand/OPT_MemoryOperand.java

public static OPT_MemoryOperand D(Address disp,
                                    byte size,
                                    OPT_LocationOperand loc,
                                    OPT_Operand guard) {
     return new OPT_MemoryOperand(null, null, (byte)0, 
disp.toWord().toOffset(), size, loc, guard);
}

In my IA32.rules file I described my operand as followed:

stm:  FS_INT_STORE(riv, OTHER_OPERAND(riv, INT_CONSTANT))
15
EMIT_INSTRUCTION
EMIT(MIR_Move.mutate(P(p), IA32_MOVFS, MO_S(P(p), DW), 
Store.getValue(P(p))));

The IA32_MOVFS opcode is similar to IA32_MOV except for it uses the fs 
data segment rather than ds. As I saw in some debug help messages, only 
MO_BD and MO_D are used and execution crashes, I think,  when a 
OPT_MemoryOperand.D is created and OPT_AssemblerBase tries to get the 
base register, and there is none. The program crashes at getBase in the 
machine generated OPT_Assembler:

 if (isRegIdx(MIR_Move.getResult(inst))) {
                    emitMOVFS_RegIdx_Imm(
                      getBase(MIR_Move.getResult(inst)), 
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), 
getDisp(MIR_Move.getResult(inst)),
                      getImm(MIR_Move.getValue(inst)));

I don't know if the BURS rule has to be modified. My question is how to 
get there, that the right emitMOVFS* instruction is used. 
OPT_AssemblerBase determines which addressing mode is used, but I do not 
understand, why isRegIdx is true, although base and index of the  
MemoryOperand are null.
Is there perhaps a problem with alias analysis? Does anybody have a 
notion, which files have to be modified? As I said in my first post I 
have no problem with the baseline compiler. Further changes I made for 
the optimizing compiler (baseline compiler changes not listed):

jikesrvm/rvm/src/vm/arch/intel/compilers/optimizing/ir/instruction/OperatorList.dat
IA32_MOVFS
MIR_Move
move


jikesrvm/rvm/src/vm/compilers/optimizing/ir/conversions/bc2hir/OPT_GenerateMagic.java
else if (methodName == VM_MagicNames.mw4) {
      OPT_Operand val = bc2ir.popInt();
      OPT_Operand addr = bc2ir.popInt();
      bc2ir.appendInstruction(Store.create(FS_INT_STORE, val, addr, new 
OPT_AddressConstantOperand(Offset.zero()), null));

jikesrvm/rvm/src/vm/compilers/optimizing/ir/instruction/OperatorList.dat
FS_INT_STORE
Store
store

jikesrvm/rvm/src/vm/runtime/VM_Magic.java
public static void mw4(int address, int value) {
    if (VM.VerifyAssertions) VM._assert(VM.NOT_REACHED);
}

jikesrvm/rvm/src/vm/runtime/VM_MagicNames.java
public static final VM_Atom mw4                           = 
VM_Atom.findOrCreateAsciiAtom("mw4");

Thank you,
Isabella