From: Stephen F. <sj...@us...> - 2002-08-28 21:00:14
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Chapman, Your description is excellent. I think the Jikes RVM implementation must serve the lowest common denominator of the architectures we run on. So, any "portable" code in Jikes RVM should use prepare-and-attempt without relying on the stronger guarantee provided by lwarx and stwcx, or else the code won't work on IA32. Similarly, it is incorrect to delete the prepare() statement and rely on attempt() to function like compare-and-swap, since this code won't work on PowerPC. SJF ------------------------------------------------------------------------ Stephen Fink IBM T.J. Watson Research Center sj...@us... (914)784-7776 Chapman Flack <fl...@ce...> Sent by: jikesrvm-researchers-admin@www-124. To: jik...@ww... southbury.usf.ibm.com cc: Subject: Re: [Jikesrvm-researchers] prepare and attempt 08/28/2002 12:51 PM Please respond to jikesrvm-researchers Hi, This gives me a chance to see if my own understanding is correct, by seeing if I can answer the question. prepare and attempt map into different instructions on different machines. On Intel, prepare is a simple load, and attempt does a compare-and-swap. The notion of conditional critical section doesn't mean much in this case; nothing special happens at the time of prepare. PowerPC has a couple nifty instructions that address a possible difficulty with compare-and-swap. CAS will succeed as long as the memory value is the same as that seen originally, _even if another processor has changed it and changed it back in the meantime_. This is an obvious argument against using a simple flag, say, and in favor of using a generation counter or something that isn't likely to wrap back to the same value by accident. PowerPC addresses the issue with a "load with reservation" instruction and a "store conditional" instruction. lwarx does not only load a value from the memory location, but sets a hardware latch that will be reset by any write to that location (or maybe any nearby location within a certain granularity, I'm not sure of the details). stwcx is a store that will succeed only if the latch is still set. This way you know you will fail if anybody else has written the location, even if it was written back to the original value. So on PowerPC, prepare and attempt map into lwarx and stwcx. A weakness of the scheme, it seems to me, is that as long as prepare/attempt map to vanilla CAS on any architecture, all algorithms that use them had better be designed to work properly with vanilla CAS; we can't depend on the PowerPC reservation feature. If that's the case, shouldn't the appropriate set of magic primitives be CAS and, perhaps, DCAS? There seems to be a consensus growing in this lab that CAS/DCAS are the primitives getting the most attention in the literature these days. Am I close? -Chap _______________________________________________ Jikesrvm-researchers mailing list Jik...@ww... http://www-124.ibm.com/developerworks/oss/mailman/listinfo/jikesrvm- researchers |