From: FUJITA T. <fuj...@la...> - 2007-06-25 03:03:54
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From: Arne Redlich <ag...@po...> Subject: Re: [Iscsitarget-devel] Proposal: New Hybrid IO Type Date: Sun, 24 Jun 2007 20:51:35 +0200 > "Ross S. W. Walker" <rw...@me...> writes: > > >> -----Original Message----- > >> From: Arne Redlich [mailto:ag...@po...] > >> Sent: Sunday, June 24, 2007 2:27 PM > >> To: Ross S. W. Walker > >> Cc: Isc...@li... > >> Subject: Re: [Iscsitarget-devel] Proposal: New Hybrid IO Type > >> > >> CMIIW: You want to bypass the page cache for WRITEs and > >> leverage it for > >> READs? You're aware that every WRITE will have to update/invalidate > >> READ-cached data? > > > > Good point. Any ideas on a way to get this to happen? Maybe madvise on > > writev? > > Then it's not direct I/O anymore (i.e. no page cache bypass), as madvise() / > posix_fadvise() changes the kernel's caching behaviour. > > Anyway, I should have put it more clearly: I don't think that bypassing > the cache for one data direction and using it for the other one is > feasible, as you will have to take care of cache consistency manually. I think > the resulting overhead really isn't worth doing it in the first place. Agreed. It just doesn't make sense. |