From: Andrei R. <ar...@ya...> - 2006-12-21 22:32:17
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Hi Dave, "missed interrupt" was rather a figure of speech than a statement of facts. I'm starting to get an idea of what might get wrong. You see, this interrupt line, once it goes high, can only be brought down by reading data registers off the chip. If interrupt isn't missed, then reading of the registers must be missing. That reading is initiated in the ISR by calling spi_async(). I must be doing something wrong setting up spi_message for the transaction. -Andrei. --- Dave Hylands <dhy...@gm...> wrote: > Hi Andrei, > > > My problem with the interrupts is that > > GPIO ints are edge-sensitive and when you > > miss an edge you're going to wait for another > > one forever... Work in progress > > I don't quite understand this. The hardware > shouldn't be missing > edges. The only issue should be if an edge occurs > while you're inside > the interrupt handler. > > The normal way that this is dealt with is that you > clear the interrupt > as the first thing in the handler, and then you go > and deal with it. > That way if an additional edge comes along while > you're handling the > previous one, it cause your interrupt handler to run > again as soon as > it exits. > > I believe that the GPIO irq handler takes care of > all this automatically. > > -- > Dave Hylands > Vancouver, BC, Canada > http://www.DaveHylands.com/ |