Re: [Genode-fx-main] Graphics controller with sdr-sdram problem

[Matthias A. <al...@rh...>]

Nick Simkin schrieb:
> Hi again. DE is necessary and it should be high when data out valid. Can 
> you explain how DE is formed? My be pixel data can't be read from frame 
> buffer.

The DE flag (data enable) is generated every time a new pixel has to be 
displayed. So it tells the VGA/DVI controller that it has to sample the 
digital input value coming from the FPGA. It is calculated in the 
npi_vga.vhd file. Could you check that run_timing is set to '1'?
If you like you could also send me a screen shot of the waveform viewer 
of Chipscope.

Did you check that the C code for initialization is that one for 25 MHz?

Matthias