From: Jeff E. <je...@un...> - 2010-01-20 23:39:27
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On Tue, Jan 19, 2010 at 05:29:49PM -0800, Peter C. Wallace wrote: > Being unable to reconfig the FPGA usually means that the FPGA is driving some > line that messes up the bridge (for example hold-holda or /ready are a couple > of fatal pins if driven wrong). When I have that problem, it usually that the > .ucf (constraint) file was not used for some reason. In this case the bitfile > has its pinout assigned willy-nilly. The pad report can be used to verify that > the generated pinout matches the constraints. I spot checked a few, including HOLD, HOLDA and READY and they're all in the location specified in 7i68.ucf. Is that the proper constraint file to use for 3x20? Does the 3x20 require non-default bitgen options (-g DONE_cycle and so on) like 7i43? I tried adding these (with the same settings I used on 7i43, for want of a better guess) in a firmware I sent privately to seb, but he hasn't been able to test it yet, and this really is just a stab in the dark, or more like hoping the next problem is the same as the previous one. Jeff |