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EM-65C02 is a micro-controller based emulator of a Western Design Center (WDC) 65C02 microprocessor which executes on a Microchip PIC24 or PIC33 micro-controller. The code uses the Flash memory, RAM and on-board peripherals to emulate a complete 65C02 'System on a Chip' (SOC).

A single chip, like the PIC24FJ256GP206 used in my first [A-Prototype] can emulate a 65C02 with a full 64K of RAM at around 1.4Mhz while one of the newer PIC24EP128GP202 chips in my [B-Prototype] can emulate a 65C02 at about 6Mhz but with only 8K RAM (between $0000 to $7FFF repeated four times) and 32K ROM ($8000-$FFFF). (The memory should be increased when the 24EP256GP202 amd 24EP512GP202 chips become available later in 2013).

Every 65C02 instruction is supported as well as decimal arithmetic mode. Normally a 65C02 system would have memory mapped peripheral but to keep the performance of the emulator as high as possible an additional instruction has been added to interact with the host device. See the [Host Interface] page for details.

The amount of memory and its organisation depends on the host processor. If the device has 'Extended Data Space' (EDS) memory then up to 64K of RAM can be emulated (with 32K initialized with ROM images on reset). Devices with no EDS memory have 32K ROM image and up to 16K RAM. The emulation code can be configured to make the peripherals present on the host processor available to the emulated device. At present only a UART and Timer have been exposed.

EM-65C02 was developed to see how well a modern micro-controller could emulate a 8-bit micro-processor.

All the materials on this site and the source code for the emulator are licensed under the terms defined in the Creative Commons Attribution-NonCommercial 2.0 License. You may use and extend the code for your own use and entertainment. You CANNOT create a commercial product from it.

Project Members:

• Andrew Jacobs (admin)