From: Keith W. <ke...@tu...> - 2002-09-25 17:34:38
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Michel D=E4nzer wrote: > On Mit, 2002-09-25 at 04:17, Michel D=E4nzer wrote: >=20 >>On Mit, 2002-09-25 at 03:52, Eric Anholt wrote: >> >>>On Tue, 2002-09-24 at 17:08, Michel D=E4nzer wrote: >>> >>>>BTW I'm just experiencing IRQ timeouts as well. In fact, no interrupt= s >>>>occur at all, and the RADEON_GEN_INT_STATUS register seems to always >>>>contain 0x00080007; interestingly, bit 16 isn't documented. Maybe tha= t's >>>>just a red herring though, and the IRQ is disabled in PCI config spac= e >>>>or something? >>>> >>>How often do you get timeouts? Does it happen with any app? I haven'= t >>>noticed any yet. >>> >>Neither did I until shortly before my last post, but now the CPU doesn'= t >>see any interrupts even though the chip seems to be generating them >>(that's why some bits in RADEON_GEN_INT_STATUS are set). Any idea what >>could be up and how to resolve it? >> >=20 > Simple, the interrupts weren't enabled in RADEON_GEN_INT_CNTL (it's > cleared on VT switches). The patch includes restoring that register in > EnterVT(), but I had lost the part where it's saved. Fixed now. Keith, = I > think you can enable IRQs in the r200 3D driver again. OK, so what was triggering the problem? q3 mode switching? Keith |