Re: [Dri-devel] caching, writecombining, framebuffers, agp

[Keith W. <ke...@tu...>]

Jeff Hartmann wrote:
> This really really sounds like a read cache problem, I saw similar behavior
> before.  I think on the Matrox cards, but my memory is abit fuzzy.  Can you
> try writing to two different locations (a least several K apart), then
> reading your values?
> 
> I would recommend trying something like the following pseudocode:
> {
> 	Sync the dma stream and wait for drawing completion
> 	Read from the very last pixel in the framebuffer, write its value back.
> 	Read from the very first pixel in the framebuffer, write its value back.
> 	Do your normal operations.
> }
> 
> If this fixes the problem you will have to reserve a pixel somewhere that
> can be destroyed.  I believe the first read/modify/write could get the wrong
> pixel value, but the second should work.
> 
> Read caches can sometimes be really weird, and might have very stale values
> sometimes.

Indeed, reading & rewriting the first pixel in the framebuffer fixes the later 
fb accesses for me.

What is going on here???  Where are these values getting cached and how does 
doing this read/write cause the cache to get flushed?

What other values could be bogus?  MMIO springs to mind, for example when 
doing wait-for-idle loops.

Keith