Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
This project is ported to github and can be found at:
https://github.com/chiphackers/covered
License
GNU General Public License version 2.0 (GPLv2)Follow Covered
Other Useful Business Software
Atera - an All-in-one platform for IT management
Your IT essentials, integrated & elevated. Take your IT management from automated to autonomous, download Atera's agent to start your free trial!
Rate This Project
Login To Rate This Project
User Reviews
Be the first to post a review of Covered!