Covered is a Verilog code coverage utility using VCD/LXT dumpfiles (or VPI simulation interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
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sf-robot commented on the stray character in inlined annotations artifact -
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phase1geo commented on the stray character in inlined annotations artifact -
Stable release 0.7.7 available
Stable release covered-0.7.7 made. This is a bug fix release only. - Fixed compilation warnings when compiling on 64-bit Mac OS X and Debian-based platforms. - Updates to build scripts to help d... -
File released: /covered-stable/covered-0.7.7/covered-diags-0.7.7.tar.gz
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