Covered
by phase1geo
Covered is a Verilog code coverage utility using VCD/LXT dumpfiles (or VPI simulation interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
Project Feed
-
Tracker comment added
sf-robot commented on the Parameterized/generated modules can get incorrect coverage artifact
-
Development release covered-20090705 available
Added support for inlined code coverage usage flow. See release notes and user guide for more information.
-
Code committed
phase1geo committed patchset 2685 of module covered to the Covered CVS repository, changing 2 files
-
Code committed
phase1geo committed patchset 2679 of module covered to the Covered CVS repository, changing 60 files
-
Code committed
phase1geo committed patchset 2678 of module covered to the Covered CVS repository, changing 125 files
-
Code committed
phase1geo committed patchset 2677 of module covered to the Covered CVS repository, changing 46 files
-
Code committed
phase1geo committed patchset 2676 of module covered to the Covered CVS repository, changing 788 files
-
Tracker comment added
sf-robot commented on the Generated module instantiations broken artifact
-
Tracker comment added
edspittles commented on the assertion failed: vector.c:816 artifact
-
Code committed
phase1geo committed patchset 2669 of module covered to the Covered CVS repository, changing 1 files
Related Projects
Covered Actions
About SourceForge
Develop Software
Copyright © 2009 SourceForge, Inc. All rights reserved. Terms of Use
