Covered is a Verilog code coverage utility using VCD/LXT dumpfiles (or VPI simulation interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
Release Date:
2009-10-25
Topic:
Operating System:
OS Independent (Written in an interpreted language),
OS Portable (Source code to work with many OS platforms)
OS Portable (Source code to work with many OS platforms)
License:
Translations:
Intended Audience:
User Interface:
Programming Language:
Registered:
2002-04-11
Ratings and Reviews
Be the first to post a text review of Covered. Rate and review a project by clicking thumbs up or thumbs down in the right column.
Project Feed
-
Code committed
-
Tracker comment added
phase1geo commented on the verilog parenthesis parsing segfault artifact -
Tracker artifact added
akreynolds created the verilog parenthesis parsing segfault artifact -
Tracker comment added
sf-robot commented on the specify CDD file for GUI on connand line artifact -
Tracker comment added
sf-robot commented on the Segmentation fault on Error messages before TCL gui runs artifact -
Tracker comment added
sf-robot commented on the parsing args via '-f' counts merge_in_num incorrectly artifact -
Tracker artifact added
Anonymous created the CEIJnUBCNZUr artifact -
Tracker artifact added
Anonymous created the AAgBFVbXcvj artifact -
Tracker artifact added
Anonymous created the nDUSTovlbYOghAL artifact -
Tracker artifact added
Anonymous created the YTlSKpVeWyJeacQEpKK artifact
Rate and Review
Be the first person to add a text review.
Related Projects
-
siga
SIGA stands for System Information GAthering. It collects various system information and outputs it in HTML or ASCII format.
-
Covered Actions
About SourceForge
Develop Software
Community
Copyright © 2009 Geeknet, Inc. All rights reserved. Terms of Use
