Covered is a Verilog code coverage utility using VCD/LXT dumpfiles (or VPI simulation interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
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Project Admins:
phase1geo
Operating System:
OS Independent (Written in an interpreted language), OS Portable (Source code to work with many OS platforms)
License:
GNU General Public License (GPL)
Category:
Electronic Design Automation (EDA)
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Latest News
- Development release covered-20080415 available 2008-04-15
- Development release covered-20080314 available 2008-03-13
- Stable release 0.6.1 now available 2008-03-13
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Bugs
: (1 open / 161 total)
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Feature Requests
: (1 open / 18 total)
Feature Request Tracking System - Public Forums : (2 messages in 2 forums)
- Mailing Lists : (2 total)
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CVS Repository
: (517 commits,
1,391 reads)
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Project Details
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Project Admins :
phase1geo
- Developers : 1
- Development Status : 5 - Production/Stable
- Intended Audience : Developers, Education
- License : GNU General Public License (GPL)
- Operating System : OS Independent (Written in an interpreted language), OS Portable (Source code to work with many OS platforms)
- Programming Language : C, Tcl
- Topic : Electronic Design Automation (EDA)
- Translations : English
- User Interface : Command-line, Tk
- Project UNIX name : covered
- Registered : 2002-04-11 16:46
- Activity Percentile (last week) : 99.36
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