Covered is a Verilog code coverage utility using VCD/LXT dumpfiles (or VPI simulation interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
Project Admins:
phase1geo
Operating System:
OS Independent (Written in an interpreted language), OS Portable (Source code to work with many OS platforms)
License:
GNU General Public License (GPL)
Category:
Electronic Design Automation (EDA)
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