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Covered

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Description

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.

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Additional Project Details

Languages

English

Intended Audience

Developers, Education

User Interface

Command-line, Tk

Programming Language

C, Tcl

Registered

2002-04-11
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