Double release day

August 3rd, 2009

Today I released a new stable and development release of Covered. The new stable release is a bug release only. The new development release builds on the last development release in regards to the new inlined code coverage scoring flow. Basic functionality was implemented in the previous development release. This new release improves both simulation and score performance in a variety of ways for inlined code coverage flows.

With this work now done, I will be focusing on splitting out the current CDD file format into multiple files for a more efficient way of handling and working with coverage information. This change is intended to make working with Covered more simple with several performance enhancements, especially for the merge and rank commands and the GUI. When these changes have been made, Covered will be switching over to the new inlined code coverage flow permanently and several command-line changes will be made to match the new data structure changes.

This is all going toward the 1.0 stable release of Covered. Lots of work and testing to do, but we are on our way! The current development release should be more stable and bug free than the previous release, so please give the new development release a try and log any bugs found.

Development release covered-20090705 now available

July 5th, 2009

Development release covered-20090705 made. This development branch adds support for a new type of code coverage scoring.  Code coverage information is embedded (inlined) in a copy of the original design files. These instrumented files can then be simulated and either a dumpfile can be generated and run through Covered’s score command or Covered can run in VPI mode with the simulator to generate a scored CDD file.

The advantage to running in this mode of operation will be more accurate coverage of the design based on the simulator being used and a lack of “resimulation” to be done by Covered. Eventually, this mode of operation will be Covered’s only method of code coverage accumulation, but this development release merely adds this as another way to run Covered (i.e., all previous code coverage methods work as they have). Use the new -inline (and optionally -inline-metrics) score options to cause the instrumented files to be output in a directory called “covered/verilog” in the directory where the Covered score command is run (see user documentation for details).

This feature is fully passing in Covered’s regression but should be considered in an alpha state at this point. In the next
development release, I am planning on adding some performance improvements for this feature, but please feel free to submit bug reports about anything related to this new feature.

Here’s a list of a few other features added:

  • Integrated all bug fixes found in the stable release of Covered.
  • Added regression support for the Veriwell simulator
  • Added initial regression support for the Vcomp simulator (however, vcomp doesn’t seem to be working well for me).
  • Added documentation to user guide for the new inlined code coverage options and usage flow
  • Verified that all code is splint clean
  • Added support for ternary operators in static expression location

Getting Started

May 6th, 2009

This is my first blog for the Covered utility. Covered is a Verilog code coverage analysis tool that allows a design verification engineer to determine how well a given test suite is exercising a given design.

Covered is aimed to be highly flexible and non-intrusive to the normal verification flow with the ability to extract coverage using a dumpfile created from a diagnostic run or using the VPI interface during a diagnostic run. Coverage databases can be merged, reported on (with either ASCII file output or via a GUI interface), and ranked. Additionally, coverage points can be excluded/included on the command-line or via the GUI, optionally allowing the user to provide a reason for the exclusion which is saved and output in coverage reports.

Covered is fully Verilog-1995 compliant, supports most of the Verilog-2001 extensions, and even supports various SystemVerilog constructs.

There is extensive documentation on using both the command-line and GUI interfaces of Covered.

I plan on using this blog site for providing various information about the development process of Covered, what’s coming up in the next release, and possibly quick tips on how to make better use of Covered’s feature set.