Algorithmix

Hey, Olaf! Thank you for your reply. Some very awesome experiments and ideas you have written about! I'll try to give some input/opinions: CPU-history I completely 1000% agree with you that it would be extremely helpful to have the "interrupt-BRK" instructions in the CPU-history as well! That would be a very valuable debugging help! And it would also better show what the CPU have been executing. (Also, i'm glad i'm not the only one who have been surprised by this xD) Right now, in your prototype,...

Hey, Olaf! Thank you for your reply. Some very awesome experiments and ideas you have written about! I'll try to give some input/opinions: CPU-history I completely 1000% agree with you that it would be extremely helpful to have the "interrupt-BRK" instructions in the CPU-history as well! That would be a very valuable debugging help! And it would also better show what the CPU have been executing. (Also, i'm glad i'm not the only one who have been surprised by this xD) Right now, in your prototype,...

Hey, Olaf! Thank you for your reply. Some very awesome experiments and ideas you have written about! I'll try to give some input/opinions: CPU-history I completely 1000% agree with you that it would be extremely helpful to have the "interrupt-BRK" instructions in the CPU-history as well! That would be a very valuable debugging help! And it would also better show what the CPU have been executing. (Also, i'm glad i'm not the only one who have been surprised by this xD) Right now, in your prototype,...

By the way, my last two posts were only about "Problem #2". I do not know the VICE sourcecode, so don't think i can give much input to the other posts. Let me know if you need something from me, of course :) TL;DR: "Problem #2" could be considered a bug or it could be considered expected behaviour, and this issue could be closed (and preferably write a couple of lines description in the monitor documentation). Also, maybe i'm missing something, so you guys should probably doublecheck my assumptions...

By the way, my last two posts were only about "Problem #2". I do not know the VICE sourcecode, so don't think i can give much input to the other posts. Let me know if you need something from me, of course :) TL;DR: "Problem #2" could be considered a bug or it could be considered expected behaviour, and this issue could be closed (and preferably write a couple of lines description in the monitor documentation). Also, maybe i'm missing something, so you guys should probably doublecheck my assumpti...

By the way, my last two posts were only about "Problem #2". I do not know the VICE sourcecode, so don't think i can give much input to the other posts. Let me know if you need something from me, of course :)

Turns out i already did this most of the test program for "Problem #2". I've looked a bit more into it today, and think i've now gotten a better understanding of what's going on - and it's not as bad as i was afraid of. This is NOW my understanding of the issue: (remember: this is just me guessing from a couple of experiments, but i do think it makes sense) For rasterline-breakpoints (an RL-condition): If you break at an instruction where an interrupt will start immediately after that instruction,...

Turns out i already did this most of the test program. I've looked a bit more into it today, and think i've now gotten a better understanding of what's going on - and it's not as bad as i was afraid of. This is NOW my understanding of the issue: (remember: this is just me guessing from a couple of experiments, but i do think it makes sense) For rasterline-breakpoints (an RL-condition): If you break at an instruction where an interrupt will start immediately after that instruction, the monitor does...