User Activity

  • Posted a comment on ticket #943 on Small Device C Compiler (SDCC)

    Regarding rotation: In SDCC we have special handling for them, they are recognized, and if the backend happens to support the specific, treated as rotations by code generation, instead of a combination of shifts, etc. For the current z80 port (and all z80-related ports): The type being rotated must have a width that is a multiple of 8, and at least one of the following must be true: The type is 8 bits wide It is a rotation by one to the left or right It is a rotation by half the width of the type...

  • Posted a comment on ticket #935 on Small Device C Compiler (SDCC)

    What I implemented turned out to work not se well, but I kept thinking about it,and in [r15006], we now have such an optimization that is much better, and also covers the case in the example code given.

  • Modified ticket #935 on Small Device C Compiler (SDCC)

    Inefficient math

  • Committed [r15006] on Code (SVN)

    Fix and improve right shift optimization, RFE #935.

  • Modified a comment on ticket #935 on Small Device C Compiler (SDCC)

    At code generation, we don't easily know that the upper bits of the right shift by 5 result will be unused. So we need to generate them. But since we could know from generalized constant propagation that we have the result of an upcast, I think for right shifts of at least 4 (for code size) or 5 (code speed), if the result is in lh, we could then generate this code: add hl, hl jr nc, 1 inc hl 1: adc hl, hl adc hl, hl adc hl, hl Then a peephole optimizer rule should be able to see that l is unused,...

  • Committed [r15005] on Code (SVN)

    Right shift optimization inspired by RFE #935.

  • Modified a comment on ticket #935 on Small Device C Compiler (SDCC)

    At code generation, we don't easily know that the upper bits of the right shift by 5 result will be unused. So we need to generate them. But since we could know from generalized constant propagation that we have the result of an upcast, I think for right shifts of at least 4 (for code size) or 5 (code speed), if the result is in lh, we could then generate this code: add hl, hl jr nc, 1 inc hl 1: adc hl, hl adc hl, hl adc hl, hl Then a peephole optimizer rule should be able to see that l is unused,...

  • Posted a comment on ticket #935 on Small Device C Compiler (SDCC)

    At code generation, we don't easily know that the upper bits of the right shift by 5 result will be unused. So we need to generate them. But since we could know from generalized constant propagation that we have the result of an upcast, I think for right shifts of at least 4 (for code size) or 5 (code speed), if the result is in lh, we could then generate this code: add hl, hl jr nc, 1 inc hl 1: adc hl, hl adc hl, hl adc hl, hl Then a peephole optimizer rule should be able to see that l is unused,...

View All

Personal Data

Username:
spth
Joined:
2002-06-16 16:36:10

Projects

This is a list of open source software projects that Philipp Klaus Krause is associated with:

  • Schlange 2   Last Updated:
  • Project Logo Small Device C Compiler (SDCC) The Small Device C Compiler (SDCC), targeting 8-bit architectures Last Updated:
  • eclipseSDCC   Last Updated:
  • lnlc lnlc calculates linear nlc-width and corresponding expressions Last Updated:
  • rw rw calculates rank-width and rank-decompositions. Last Updated:

Skills

This is a list of skills that Philipp Klaus Krause possesses:

  • C
  • C++
  • Assembly
  • Scheme

Personal Tools