RvD

I guess there is some way to enable support for 32-bit relocations currently missing? Is this a question to me or other maintainers? I don't have an answer for that. I'm a bit confused by this, though: AFAIK, we only have an 8-bit address space for __sfr? I think that is correct. So shouldn't that be a 32-bit wide sfr at 0xa7 to 0xaa (with SDCC emitting a warning that 0xa3a5a6a7 is out of sfr range)? So this would actually be a compiler issue for even trying to emit those shifts to get the upper...

I guess there is some way to enable support for 32-bit relocations currently missing? Is this a question to me or other maintainers? I'm a bit confused by this, though: AFAIK, we only have an 8-bit address space for __sfr? I think that is correct. So shouldn't that be a 32-bit wide sfr at 0xa7 to 0xaa (with SDCC emitting a warning that 0xa3a5a6a7 is out of sfr range)? So this would actually be a compiler issue for even trying to emit those shifts to get the upper bytes of the address? I'm not an...

I also see it in reverse mov a, (SFR_DATA_U32), E5 FF. FF location should A4 4359: 029675 E5 A7 [12] 4359 mov a,((_SFR_DATA_U32 >> 0) & 0xFF) 4361: 029678 E5 A6 [12] 4361 mov a,((_SFR_DATA_U32 >> 8) & 0xFF) 4364: 02967C E5 A5 [12] 4364 mov a,((_SFR_DATA_U32 >> 16) & 0xFF) 4367: 029680 E5 FF [12] 4367 mov a,((_SFR_DATA_U32 >> 24) & 0xFF) and in the lst-file it get this notation 106 ;-------------------------------------------------------- 107 107 ; special function registers 108 108 ;--------------------------------------------------------...

I see that the main.c has changed A4 into A3 but still the same issue. It keeps generating F5 FF.

sfr32 MSB instruction address is wrong

Two inline assembly issues.