User Activity
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Created
ticket #350
on
LIRC
lrcrcd spins on poll with 0 duration timeout
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Posted
a comment
on
ticket #947
on
Icarus Verilog
When I use that workaround in the original code, I get 'internal warning: NetCAssign::nex_input()...
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Posted
a comment
on
ticket #947
on
Icarus Verilog
This bug is reduced from a form found in the Xilinx simulation libraries. If they...
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Modified
a comment
on
ticket #947
on
Icarus Verilog
This is the same test program, but with the 'assign #100 delay_2 = delay_1;' removed....
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Posted
a comment
on
ticket #947
on
Icarus Verilog
This is the same test program, but with the 'assign #100 delay_2 = delay_1;' From...
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Created
ticket #947
on
Icarus Verilog
Reading value effects it
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Posted
a comment
on
ticket #946
on
Icarus Verilog
Thanks, I verified that this also works on the original code where I had the fai...
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Posted
a comment
on
ticket #946
on
Icarus Verilog
Also, debugging problems like this is really difficult for someone unfamiliar with...
Personal Data
- Username:
- russd
- Joined:
- 2000-02-05 23:35:07
Projects
This is a list of open source software projects that Russ Dill is associated with:
- Embedded Linux Project Last Updated:
- blob, a StrongARM boot loader Last Updated:
