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QEvt initialization requires updates in lwip example

QEvt initialization requires updates in lwip example

A quick update to my previous post: I have tested the cortex-r port on the TMS570LC43x with the TI compiler and both QV & QK kernels work with out issue. I had to regenerate the HALCoGen side of things but can't recall any major changes to the QP/C port itself.

Hello Harry, Just wanted to check if you had made some progress on the port? Just in case you were planning to open source that. Thanks!

Thanks, Miro, appreciate these comments. From a quick read, it seems to me that the MPU in TMS570L matches very well the way the "memory isolation" feature is designed in QP. Great. To understand this a little better, would the bulk of the setup just happen directly with the tools provided by TI (e.g., HALCoGen)? Those allow the specific settings (cached or not, shared or not, etc.) and protections for each of the memory regions. How would the settings by QP relate to those? Or are those to be considered...

Thanks, Miro, appreciate these comments. From a quick read, it seems to me that the MPU in TMS570L matches very well the way the "memory isolation" feature is designed in QP. Great. To understand this a little better, would the bulk of the setup just happen directly with the tools provided by TI (e.g., HALCoGen)? Those allow the specific settings (cached or not, shared or not, etc.) and protections for each of the memory regions. How would the settings by QP relate to those? Or are those to be considered...

Thanks, Miro, appreciate these comments. From a quick read, it seems to me that the MPU in TMS570L matches very well the way the "memory isolation" feature is designed in QP. Great. To understand this a little better, would the bulk of the setup just happen directly with the tools provided by TI (e.g., HALCoGen)? Those allow the specific settings (cached or not, shared or not, etc.) and protections for each of the memory regions. How would the settings by QP relate to those? Or are those to be considered...

Thanks, Miro, appreciate these comments. From a quick read, it seems to me that the MPU in TMS570L matches very well the way the "memory isolation" feature is designed in QP. Great. To understand this a little better, would the bulk of the setup just happen directly with the tools provided by TI (e.g., HALCoGen)? Those allow the specific settings (cached or not, shared or not, etc.) and protections for each of memory regions. How would the settings by QP relate to those? Or are those to be consdiered...