john munch

It should be all Sfr's! EIE2 |= E2_MAT; // enable port match interrupt now compiles for MCS51 as: mov r6,_EIE2 mov r7,#0x00 orl ar6,#0x02 mov _EIE2,r6 instead of: orl _EIE2,#0x02 which not only makes it less efficient but also makes it non-atomic which can be a major problem when enabling/disabling interrupts in interrupt service routines. All this caused some of my boards to hang after a few hours when I upgraded. Yes, there are workarounds. I chose to change 0x02 to (unsugned char)0x02 in the define...

I still think there is an issue. I have been using SDCC for a long time and really love it!! I have boards in service using the Atmel AT89C51, the AT89LP51 and the Silicon Labs EFM8SB. I had just assumed that SDCC didn't know how to initialize XRAM and so wrote my code to not depend on it. Now, I have more insight and realize it would, except that I have not configured correctly. However, the AT89C51 has dual DPTR's and no equivalent of XPAGE, the AT89LP51 has both and the EFM8SB has no dual DPTRS...

Yup: adding: Sfr(_XPAGE, 0xAA); // Point to the EMI0CN register to my si_EFM8SB2.h file and Sfr(_XPAGE, 0xF6); // Point to the PAGE register to my at89lp51xy2.h file does the trick for both. I'm not quite sure how I would have known to do that. Is there a guide to setting up such a file for a new MCS51 varient?

Oops, I accidentally left debug code (references to count) in the code. Here are the corrected ones.

Init code for MCS51 XRAM uses chip specific features.