Hi, I'm short on cycles and the current implementation adds a jump. test code for carry. : t2 [ cs, if, nop, nop, nop, then, wdr, ] ; generating: 08 f0 03 c0 00 00 00 00 00 00 a8 95 08 95 00 00 Disassembling: .data:00000000 08 f0 brcs .+2 ; 0x00000004 .data:00000002 03 c0 rjmp .+6 ; 0x0000000a .data:00000004 00 00 nop .data:00000006 00 00 nop .data:00000008 00 00 nop .data:0000000a a8 95 wdr .data:0000000c 08 95 ret .data:0000000e 00 00 nop it would be ideal if the rjmp wasn't there. plain brcs or...