Activity for Dietmar Warning
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Dietmar Warning posted a comment on ticket #829
I think the problem is more complex to solve it with the proposed fix. I used fftw3 enabled. The first picture show the plot with actual git code and the provided test case (4ms). The second is the modified code in com_fft. The signal landed in wrong bin. Both results show an amplitude error because dividing by wrong sample count.
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Obviously the fft scale is buggy. We have to check this in different functions, not only in com_fft. BTW - one question to your proposal: span = time[length-1] - time[0]; if (length > 1) { span += time[1] - time[0]; } Why add the first interval instead using the last? span = time[length] - time[0];
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Thanks for testing this problem. But your proposal gives for the pathological case length=1 still a span of 0.
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Can't see the pictures. Former post was OK.
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I think it has to be checked with gcc and msc++ too. And may be the originator of this library https://tesch1.gitlab.io/cppduals is a better address.
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Can you please provide an exported netlist from xschem. It would make the life easier.
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The structure of your testbench is unusual and wrong: control section and swept voltage source inside subckt. Please break down your testcase to a much simpler spice netlist to demonstrate your problem. Schematics and PDF doc's will not help. Attached is a similar script for gm-Id plot. Perhaps it helps.
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Correct vgs assignment - bug found by K. OHara
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You meant vdmosconf.c. l.85 and this is done last year with commit 8c3d4d79. I will look regarding the bug in vgs equation. Thank you.
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In which line is the missing VDMOStype in vdmosload.c?
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remove redundant definition and unused variable
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Arpad, it is done as mentioned. Thanks
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Minor change that helps VADistiller
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Minor change that helps VADistiller.
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convert to lower case for spice2 input and remove few warnings
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rm ngnutmeg from build list of old apps
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Hi Arpad, is it the only place to require new local variable? Or do we have this problem in other models too? I would prefer to rename cdeq to cdeqsw as local in this diode case.
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OK - is a bit fuzzy, but it works. In the book (not in the paper) is a prefactor alfa before lteratio (ltetrtol) less one and time point spacing and integration method dependent. In the table on p. 188 stands lteratio between 3.5 (default) and 10 (conservative).
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I made few trials under win11/VS22, but not any of this circuits works: examples\klu\Circuits\85\c7552\c7552.net examples/soi/ring51_40.sp example/vdmos/100W.sp examples/vbic/DFF_Y_ECL.sp Made few attempts with ltetrtol=default and 10. The simulation stops immediately with different errors. BTW: I have not the book available but in a public paper (attached) from Ken Kundert he said that the TRTOL from voltage based LTE formulae is equivalent to lteratio from spectre. And in there manual I see values...
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Regarding my post and the mentioned bug: Even the published curves Ids=f(Vgs,Vds=50V) are measured with pulsed equipment and so w/o selfheating it is possible to make temperature sweeps also with thermal switched ON models. VDMOS temperature test M1 D G 0 tj tc IRFP240 thermal VG G 0 4V VD D 0 50V .model IRFP240 VDMOS nchan + Vto=4 Kp=5.9 Lambda=.001 Theta=0.015 ksubthres=.27 + Rd=61m Rs=18m Rg=3 Rds=1e7 + Cgdmax=2.45n Cgdmin=10p a=0.3 Cgs=1.2n + Is=60p N=1.1 Rb=14m XTI=3 + Cjo=1.5n Vj=0.8 m=0.5...
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more realistic default values for case to ambient thermal resistance and device transconductances
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Adapt VDMOS Vth temperature coefficient to usual notation with - for nch and + for pch.
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Actual pre-master-46 show correct temperature dependency - see attachments. But it is not in line with my notation in my post before. |Vth| and gain goes down with rising temperature for both channel types. Because this seems a typical temperature dependency I would prefer to change this in next release. BTW - there is another bug in the model: switching on thermal model removes temperature dependency for temp sweep. Thought that I repaired this already.
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If I remember right I followed at most the discussion DiY forum VDMOS. I think the work from Ian Hegglun is the best for VDMOS modelling and parametrization I know. So I used his library (ltspice focussed) for most test cases. In his library for devices of different manufacturers I see this rules: nch VtoTC negativ pch VtoTC positiv resistor coefficients positive Exponent for mobility (gain) of both types: negative means decreasing current wit increasing temperature In my experience the temperature...
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Can confirm: The segfault is a subsequent fault in fft because tran is not successful. Tried to decrease the thermal resistances but no luck.
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Only an idea: You have v(fosc) in your write command and I assume it is a vector over the entire time duration. Try to separate these from your scalar results.
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Diode sensitivity analysis: Exclude few parameters and add level 3 geometry parameter.
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Fix the overlap in state vector for sensitivity states of diode and bjt model.
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KLU bindings for separate sw diode only if sw resistor is given
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Diode model level=2 (Fowler-Nordheim) is not supported.
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diode discontinuity
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Problem fixed by commit c1acc44 in pre-master-46.
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This fixed #822 diode discontinuity problem
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diode discontinuity
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Add optional switch for separate bottom and sidewall diode model - configuration is dependent from model parameter RSW
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add new separate diode model option
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reorder calculation sequence
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Merge request is applied into pre-master-46
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Fixed double temperature scaling.
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Merge request is applied into pre-master-46
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More VDMOS fixes
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Inconsistent behavior in VDMOS thermal model
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Latest vdmos commit fixed the problem.
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general vdmos update
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more reasonable branch name
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respect device temperature alternative to ckt temperature
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Apply A. Buermen's fix for correct thermal capacitance Cthj store in state vector
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This is already done in branch dw_vdmos and will be supplied in one commit to pre-master-46.
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apply A. Buermen's patch for correct m scaling
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VDMOS: apply m scaling fix for acld as well
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Thanks Arpad for the corrections of vdmos m scaling. Seems I missing the mentioned email. Please be aware my branch dw_vdmos with few corrections in the thermal model like threshold voltage and source resistance temp feedback.
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VDMOS scaling fixed
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Fallback to optran not needed and
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vdmos convtest needs type for vd - load hack not needed anymore
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add Rsource temperature dependency for selfheating effect
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rename rs in rb to prevent confusion with source resistor
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add Vth temperature dependency for selfheating effect
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correct dT derivatives of Beta and drain resistance
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vdmos: in case temp and dtemp is given - use dtemp and omit temp
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correct gate and source resistor temperature update
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correct rthca connection
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Even they are commented out: All your files contain non-ASCII character. The problem you have is that you try to change model parameter (ni) on instance line. This is with our osdi interface not possible. Look in the manual for altermod command. Something like this should work: altermod @diodeva[ni]=1
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correct rthca connection for KLU
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correct rthca connection
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VDMOS: few precise definitions regarding thermal model implementation
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vdmos: in case temp and dtemp is given - use dtemp and neglect temp
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prevent uninitialized warning
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correct dT derivatives and add dVth_dT
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Revert "Remove instance parameter temp. To specify offset to ambient temperature use dtemp instead."
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Revert "correct and simplify temp derivatives"
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correct and simplify temp derivatives
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Inconsistent behavior in VDMOS thermal model
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A fix is provided in pre-master-46. Please use dtemp instance parameter to apply an offset to ambient temperature.
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Remove instance parameter temp. To specify offset to ambient temperature use dtemp instead.
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Thanks for this report and test cases. I just started to investigate the problem. I think at first we have a confusion about the role of instance parameter temp and voltage on node tj. Latter shows more or less the overtemperature of the device to ambient temperature. So to make a compare usage of dtemp instead of temp instance parameter is preferable. But anyway a difference persist because of a wrong double temperature update for beta (and other variables) in case of selfheating. Removing this...
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Removing IPC is a bit pity. Sockets are still a fast and comfortable interface. Used it earlier for a different simulator - optimizer application. AFAIK, code is only in few xspice files. But if important code like dctran will be more readable I aggree to remove the ipc stuff as well. Giles Atkinson gatk555@users.sourceforge.net schrieb am Sa., 18. Okt. 2025, 02:30: That always looked like dead code to me, but I was not entirely sure. Removing it seems an excellent idea. Remove CLUSTER and IPC Sent...
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Thank you Justin, I couldn't it better say.
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I can confirm the problem. But I can't debug it in next 3 weeks. Perhaps Holger can help in the meantime.
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correct init state vector for qth integration
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@stekulov : In case there is still an interest, could you checkout ngspice development branch diode-soft-recovery compile it and check it with your test cases. My tests show at most identical results as coming from qspice and ltspice. Your opinion is welcome.
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xom and xoi overlap thickness default in Angstrom
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count poly and metal capacitances for charge calculation
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count level=3 model poly and metal capacitance in charge calculation normal operation
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count level=3 model poly and metal capacitance in charge calculation and correct xoi and xom units to Angstrom
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AFAIK skywater PDK is using .option scale=1.0u Is it setted in the failing schematic/netlist?
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diode xoi and xom parameter have unit Angstrom
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correct xoi and xom defaults to Angstrom and clarify comments
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count level=3 model poly and metal capacitance in charge calculation
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add diffusion capacity to ac relevant capacitor
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complete KLU bindings
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first trial KLU bindings
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add device informations
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first trial for ac implementation
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reverse recovery: safe guard against VP=0
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simplify branch condition
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formatting
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add modification notice
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Merge commit 'fef64ab241973fb5b937777c904649a31b52d6c3' into pre-master-46
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separate dc current for diffcharge
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trial with qd node
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