Amal Banerjee

Thanks for the useful hints. Using a combination of experimentation and small 'what-if modifications to both my netlust and the downloaded EPC2216 behavioral SPICE model, I could get the H bridge to work for this device - check attachment. As for the Yransphorm TPS*** HEMT, the Ngspice simulation is having issues with a junction FET (NJF) device mode, so I will tackle that nest.

Could some Ngspice guru here provide some hints ? Recently, I downloaded two AlGaN-GaN power models, one from EPC and one from Transphorm. I had previously created and successfully tested transient analysis of a H bridge circuit using level 3 MOSFETs. With the downloaded behavioral AlGaN-GaN HEMT models, I keep getting "timestep too small" runtime errors, for transient analysis, when I substitute the level 3 MOSFETs with the HEMTs in the H bridge netlist. Separate DC analysis of the HEMTs works fine...

Dear Ngspice gurus. I am totally clueless about the results that I get from a CMOS inverter that uses a 50 nanometeragte length NMOS and a 50 nanometer gate length PMOS. I have used both a piecewise linear (PWL) input and a PULSE input, but the results are the same. I am using the BSIM 4.8.2 level 54NMOS, PMOS models bulit into Ngspice that comes bundled with RedHat Fedora Linux 41. The netlist is below, the results are in the attachment. TEST .model n1 nmos level=54 version=4.8.2 .model p1 nmos...

Dear Ngspice gurus. I created two versions of a 8 bit serial in-serial out shift register each with a 400 MHz clock. The first version uses garden variety Level 3 MOSFETs, with a fixed gate length of 1.0 micron. The second version uses the built-in BSIM 4.8.2 Level 54 MOSFETs with 0.085 micron gates. The transient analysis results with the Level 3 MOSFETs look good, though not perfect. The transient analysis results with BSIM 4.8.2 Level 54 MOSFETs, only contain the clock signal, NONE of the input...

Dear Sir, Please take a look at my posts a few weeks ago. In those posts, I had asked(with netlists included) if someone could provide some hints about the strange results that I had obtained at that time(also included with those posts). Unfortunately, I did not receive any meaningful answers to the queries that I had at that time. So, I re-worked the problem, and the results are for all to see. Reading from, writing to a DRAM cell is tricky, No clock signals are used, instead a set of signals, very...

Dear All, DRAM cell data reads and writes using both BSIM 4.8.2 Level 54 and plain garden variety level 3 are in the attached document. Please check the attachment.

Without getting into discussion about sense amplifiers, please explain why: with the drain at a higher bias than the source (0.5V at drain, 0.0 V at source) the when the positive gate bias pulse is applied, the MOSFET is unable to conduct, i,e,, reduce the drain bias to a lower value. If the drain bias was reduced, but not fully pulled down to 0.0 V, then it would a case of the MOSFET not having sufficient current drive. I have four BSIM level 54 version 4.8.2 nMOS in parallel, so there must be at...

Dear Ngspice gurus. Please kindly check the attached PDF file. The simplest DRAM cell(MOSFET with storage capacitor on source) allows writes, but no reads. Any hints, suggestions would be very helpful. Thanks in advance.