Activity for Cary R.
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Cary R. posted a comment on ticket #52
Hi Srini, We normally only use SourceForge for the mailing list and for release distribution. I think Steve requested you to use to discuss this on the mailing list. Please post this to the iverilog-devel mailing list. The short answer is look at ivtest which is our regression environment and determine how to integrate your tests into that environment. For your development I completely understand your desire to have your tests Makefile driven and it should be possible to architect your tests so they...
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You need to clock on the edit link. I updated it to VHDL since I assume that is what you were trying to do.
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VHDL: rotate support for simulation
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Is this for VHDL? If so please add VHDL to the beginning of the title.
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iverilog creates infinite loop
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I can confirm that both V10 and devel are advancing in time, but the simulations did not produce any output or finish. V0.9 did produce output and completed.
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vvp incorrectly exits on termination of a begin/end
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I can confirm V10 produces different results then devel which produced the following: Incr/decr operators... line 91, CHECK_RES line 91-1, CHECK_RES line 91-2B, CHECK_RES line 91-B, cleared $ID111 line 91-C, done line 91: completed line 92, CHECK_RES line 93, CHECK_RES line 94, CHECK_RES line 100, arithmetic line 103, CHECK_RES in $L59... incr passcount... done test complete: 30 passes, 0 fails Which is more than you indicated above.
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Program fails until a $write debug statement is added
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I cannot reproduce the problem using the latest version of 10 or devel I get the expected results with the $write line commented out. It looks like you are using the latest 10 version so this discrepency is odd.
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This all sounds reasonable since that is what other simulators are doing. Now the...
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I have applied the patch to both development and V0.9. I will push a test program...
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segfault in vvp processing events with fst dumper
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OK, you and Cary are saying that the always block may or may not complete execution...
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The sensitivity list consists of one or more signals. When at least one of these...
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"why wouldn't this trigger the always block to be executed?" Read my follow up post...
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And changing the #11 to #9 will not miss a trigger.
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I just read your replies again and I think this is the crux of the problem. "I'm...
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I looked at pages 5 and 6 of the paper. They just describe the stratified event queue...
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I don't see the attachment you are referring to. Giving the name of the paper may...
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Since most Verilog simulators are single threaded only one block is usually execute...
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Thanks Larry. Reminder to self. Remember to do a make clean when messing with a Makefile...
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A fix that should fix this has been pushed. A build dependence was missed. Since...
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Try to eliminate spurious -dirty in version_tag.h
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This looks reasonable and I have applied the patch.
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This is also failing for the development branch so I'm switching this bug to development....
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vvp_process.c: Assertion failed: number_is_immediate
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Spelling fixes
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VHDL enum values not available outside of switch statements
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VHDL enum type declaration generates syntax errors
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We have added a test for this problem to the test suite and it is now working again...
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VHDL enum values not available outside of switch statements
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A test for this problem has been added to the test suite.
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VHDL enum type declaration generates syntax errors
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A test for this problem has been added to the test suite.
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There are plans to add this functionality, but it takes time and we don't always...
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Patch applied and pushed.
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Add -Wstrict-prototypes to CFLAGS
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display.cc:85: bad assert
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It took me a bit to find this. It is actually in V0.9 not development. In development...
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Note that the second example has a race in that the initialization of value and the...
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Thanks. I can confirm I get the same results as you do. This is likely complicated...
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Passing inout values to submodules
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Like Martin, I also just checked this with the same results. It worked as I expected....
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I have added the file and line information and an error message that reports this...
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Thank you for the report and reduced example. I have verified that this is still...
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SDF back annotation fails/aborts for a tri-state buffer
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I have pushed a fix for the final issue that your test code uncovered. There have...
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sv package enumerated type and function
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Actually not only is it supported, but Icarus already does this correctly. The real...
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Okay this is supported and like I assumed the delay is to be applied to every delay...
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How it helps is that it confirms my assumption that the SDF has non-conditional delays...
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What do the SDF lines look like? I just checked the code and it looks like it correctly...
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I wanted to focus on the asserts first. Now that they have been taken care of I want...
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Okay, Let's ignore the actual tri-state cells for now and try to figure out the rest...
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For us pushed refers to actually pushing the fix to github versus testing it in our...
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Okay, that's what I was expecting. I think my test code is reproducing the bug you...
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You missed me asking if there was a matching scope with ModPort statements. In a...
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I have an example that is giving the same messages and it looks like the compiler...
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You did not provide the ModPath section, but from what you did show it looks like...
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To verify this look in the output from the compiler... This comment is referring...
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Interesting. From your output it truely does imply that there is no ModPaths for...
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Yes I understand, not everyone is multi-lingual. In the previous message I said I...
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The problem with the current assert location is we do not have this information....
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After I pushed the patch I realized I forgot to add support for a single delay and...
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SDF back annotation fails/aborts for a tri-state buffer
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In looking at this. The empty delay code is working correctly. I initially made a...
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SDF back annotation fails/aborts for a tri-state buffer
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I can reproduce the assert. I am not currently getting any warnings so something...
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This should be enough. I'll try to build a working example from this input so that...
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It would be easiest for us if we had the instantiation line and the appropriate SDF...
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Hi Eric, That is correct interfaces are not currently supported. We may have someone...
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I have pushed a fix for this issue.
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Class method cannot call other class methods
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Class method cannot call other class methods
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Unable to successfully import a class from a package.
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No support for SV compilation unit classes, tasks or functions
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I have pushed a patch that fixes some of the issues your code uncovered. The remaining...
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sv package enumerated type and function
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I am looking at this issue. I am confused by your comment saying that moving the...
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Easy changes for -Wmissing-prototypes
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Patch applied and pushed
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I have applied and pushed this patch.
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Eliminate a few more easy warnings
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Fully initialize a couple structures
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I have applied and pushed this patch.
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This all looks reasonable. I have applied and pushed this patch. It would be nice...
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Rearrange compiler warning flags
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More fussing with C function prototypes
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Patch applied and pushed.
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Fuss with C function prototypes
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Patch applied and pushed.
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I have pushed a fix for this to git and it will be available in V0.9.8 whenever it...
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Problem of index in a generate block
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The issue here is that V0.9 uses eval_const() when calculating the constant for a...
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Just as a note, there is an error in the code for the 2 to 1 mux module. The term...
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I can confirm that this is still failing with the latest V0.9 from git. It does compile...
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Clean up some more sign-compare issues
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I have pushed this patch. I will update the comment in the configure script to note...
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I agree and I noticed that inconsistency as well. I think the original reluctance...
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