KooLee

FPGA info for Vivado Name Fpag_0_Value Fpag_1_Value REGISTER.IR 010101 110101 REGISTER.IR.BIT0_ALWAYS_ONE 1 1 REGISTER.IR.BIT1_ALWAYS_ZERO 0 0 REGISTER.IR.BIT2_ISC_DONE 1 1 REGISTER.IR.BIT3_ISC_ENABLED 0 0 REGISTER.IR.BIT4_INIT_COMPLETE 1 1 openocd 0.10.0 debug logs User : 13 2 options.c:63 configuration_output_handler(): debug_level: 3 User : 14 4 options.c:63 configuration_output_handler(): Debug: 15 5 options.c:187 add_default_dirs(): bindir=/usr/local/bin Debug: 16 7 options.c:188 add_default_dirs():...

FPGA info for Vivado Name Fpag_0_Value Fpag_1_Value REGISTER.IR 010101 110101 REGISTER.IR.BIT0_ALWAYS_ONE 1 1 REGISTER.IR.BIT1_ALWAYS_ZERO 0 0 REGISTER.IR.BIT2_ISC_DONE 1 1 REGISTER.IR.BIT3_ISC_ENABLED 0 0 REGISTER.IR.BIT4_INIT_COMPLETE 1 1 openocd 0.10.0 debug info User : 13 2 options.c:63 configuration_output_handler(): debug_level: 3 User : 14 4 options.c:63 configuration_output_handler(): Debug: 15 5 options.c:187 add_default_dirs(): bindir=/usr/local/bin Debug: 16 7 options.c:188 add_default_dirs():...

FPGA info for Vivado Name Fpag_0_Value Fpag_1_Value REGISTER.IR 010101 110101 REGISTER.IR.BIT0_ALWAYS_ONE 1 1 REGISTER.IR.BIT1_ALWAYS_ZERO 0 0 REGISTER.IR.BIT2_ISC_DONE 1 1 REGISTER.IR.BIT3_ISC_ENABLED 0 0 REGISTER.IR.BIT4_INIT_COMPLETE 1 1

J-link.cfg adapter driver jlink adapter speed 15000 transport select jtag xc7.cfg add jtag newtap xc7_2 tap -irlen 2 -expected-id 0x13631093 scan_chain openocd 0.10.0 log jtag xc7_program Info : Listening on port 6666 for tcl connections Info : Listening on port 4444 for telnet connections Warn : Failed to open device: LIBUSB_ERROR_NOT_SUPPORTED. Info : J-Link V9 compiled May 7 2021 16:26:12 Info : Hardware version: 9.60 Info : VTarget = 3.314 V Info : clock speed 15000 kHz Info : JTAG tap: xc7.tap...

Try to connect using the JLink programmer jtag xc7_program Info : Listening on port 6666 for tcl connections Info : Listening on port 4444 for telnet connections Warn : Failed to open device: LIBUSB_ERROR_NOT_SUPPORTED. Info : J-Link V9 compiled May 7 2021 16:26:12 Info : Hardware version: 9.60 Info : VTarget = 3.303 V Info : clock speed 15000 kHz Info : JTAG tap: xc7.tap tap/device found: 0x13631093 (mfg: 0x049 (Xilinx), part: 0x3631, ver: 0x1) Info : JTAG tap: auto0.tap tap/device found: 0x13631093...

How to Select Daisy Chain Chip Devices

Thanks for your reply, but I don't quite understand the jtagspi cmd commands. Take is25lp128f flash chip as an example, I want to set the value of status register Bit6 QE to 1. Can you tell me the sample code, thanks a lot. :)

Modify the FPGA flash status register